Network Calculus has been a foundational theory for analyzing and ensuring Quality-of-Service (QoS) in a variety of networks including Networks on Chip (NoCs). To fulfill dynamic QoS requirements of applications, runtime application of network calculus is essential. However, the primitive operations in network calculus such as arrival curve, min-plus convolution and min-plus deconvolution are very time consuming when calculated in software because of the large volume and long latency of computation. For the first time, we propose a configurable hardware architecture to enable runtime application of network calculus. It employs a unified pipeline that can be dynamically configured to efficiently calculate the arrival curve, min-plus convolution, and min-plus deconvolution at runtime. We have implemented and synthesized this hardware architecture on a Xilinx FPGA platform to quantify its performance and resource consumption. Furthermore, we have built a prototype NoC system incorporating this hardware for dynamic flow regulation to effectively achieve QoS at runtime.

网络演算已成为分析和确保各种网络（包括片上网络（NoC））中的服务质量（QoS）的基础理论。为了满足应用程序的动态QoS要求，网络演算的运行时应用程序必不可少。但是，由于计算量大且等待时间长，因此在软件中进行计算时，网络演算中的原始运算（例如到达曲线，最小加卷积和最小加反卷积）非常耗时。首次，我们提出了一种可配置的硬件体系结构，以启用网络演算的运行时应用程序。它采用统一的流水线，可以动态配置该流水线，以在运行时有效地计算到达曲线，最小加卷积和最小加反卷积。我们已经在Xilinx FPGA平台上实现并综合了这种硬件架构，以量化其性能和资源消耗。此外，我们已经构建了一个原型NoC系统，该系统结合了用于动态流调节的该硬件，以在运行时有效地实现QoS。