The Arm Triple Core Lock-Step (TCLS) architecture is the natural evolution of Arm Cortex-R Dual Core Lock-Step (DCLS) processors to increase dependability, predictability, and availability in safety-critical and ultra-reliable applications. TCLS is simple, scalable, and easy to deploy in applications where Arm DCLS processors are widely used (e.g., automotive), as well as in new sectors where the presence of Arm technology is incipient (e.g., enterprise) or almost non-existent (e.g., space). Specifically in space, COTS Arm processors provide optimal power-to-performance, extensibility, evolvability, software availability, and ease of use, especially in comparison with the decades old rad-hard computing solutions that are still in use. This article discusses the fundamentals of an Arm Cortex-R5 based TCLS processor, providing key functioning and implementation details. The article shows that the TCLS architecture keeps the use of rad-hard technology to a minimum, namely, using rad-hard by design standard cell libraries only to protect the critical parts that account for less than 4% of the entire TCLS solution. Moreover, when exposure to radiation is relatively low, such as in terrestrial applications or even satellites operating in Low Earth Orbits (LEO), the system could be implemented entirely using commercial cell libraries, relying on the radiation mitigation methods implemented on the TCLS to cope with sporadic soft errors in its critical parts. The TCLS solution allows thus to significantly reduce chip manufacturing costs and keep pace with advances in low power consumption and high density integration by leveraging commercial semiconductor processes, while matching the reliability levels and improving availability that can be achieved using extremely expensive rad-hard semiconductor processes. Finally, the article describes a TRL4 proof-of-concept TCLS-based System-on-Chip (SoC) that has been prototyped and tested to power the computer on-board an Airbus Defence and Space telecom satellite. When compared to the currently used processor solution by Airbus, the TCLS-based SoC results in a more than 5× performance increase and cuts power consumption by more than half.

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Arm 三核锁步 (TCLS) 处理器

Arm 三核锁步 (TCLS) 架构是 Arm Cortex-R 双核锁步 (DCLS) 处理器的自然演进，旨在提高安全关键和超可靠应用的可靠性、可预测性和可用性。TCLS 简单、可扩展且易于部署在广泛使用 Arm DCLS 处理器的应用（例如，汽车）中，以及在 Arm 技术刚刚起步或几乎不存在的新领域（例如，企业）中。例如，空间）。特别是在太空领域，COTS Arm 处理器提供了最佳的功率性能比、可扩展性、可进化性、软件可用性和易用性，尤其是与几十年前仍在使用的抗辐射计算解决方案相比。本文讨论了基于 Arm Cortex-R5 的 TCLS 处理器的基础知识，提供关键功能和实施细节。文章表明，TCLS 架构将 rad-hard 技术的使用保持在最低限度，即仅使用 rad-hard by design 标准单元库来保护占整个 TCLS 解决方案不到 4% 的关键部分。此外，当辐射暴露相对较低时，例如在地面应用中，甚至在低地球轨道 (LEO) 中运行的卫星中，该系统可以完全使用商业小区库来实施，依靠 TCLS 上实施的辐射缓解方法来应对在其关键部分有零星的软错误。因此，TCLS 解决方案可以通过利用商业半导体工艺显着降低芯片制造成本，并跟上低功耗和高密度集成的进步，同时匹配可靠性水平并提高使用极其昂贵的抗辐射半导体工艺可以实现的可用性。最后，本文描述了一种基于 TRL4 概念验证的基于 TCLS 的片上系统 (SoC)，该片上系统 (SoC) 已经过原型设计和测试，可为空中客车国防和太空电信卫星上的计算机供电。与空客目前使用的处理器解决方案相比，基于 TCLS 的 SoC 可将性能提升 5 倍以上，并将功耗降低一半以上。这篇文章描述了一种基于 TRL4 概念验证的基于 TCLS 的片上系统 (SoC)，它已经过原型设计和测试，可为空中客车国防和太空电信卫星上的计算机供电。与空客目前使用的处理器解决方案相比，基于 TCLS 的 SoC 可将性能提升 5 倍以上，并将功耗降低一半以上。这篇文章描述了一种基于 TRL4 概念验证的基于 TCLS 的片上系统 (SoC)，它已经过原型设计和测试，可为空中客车国防和太空电信卫星上的计算机供电。与空客目前使用的处理器解决方案相比，基于 TCLS 的 SoC 可将性能提升 5 倍以上，并将功耗降低一半以上。