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New paradigm of FPGA-based computational intelligence from surveying the implementation of DNN accelerators
Design Automation for Embedded Systems ( IF 1.4 ) Pub Date : 2022-01-12 , DOI: 10.1007/s10617-021-09256-8
Yang You 1 , Hongyin Luo 1 , Xiaojie Liu 1 , Bijing Liu 1 , Kairong Zhao 1 , Shan He 1 , Lin Li 1 , Donghui Guo 1 , Yinghui Chang 2 , Weikang Wu 2 , Bingrui Guo 3
Affiliation  

With the rapid development of Artificial Intelligence, Internet of Things, 5G, and other technologies, a number of emerging intelligent applications represented by image recognition, voice recognition, autonomous driving, and intelligent manufacturing have appeared. These applications require efficient and intelligent processing systems for massive data calculations, so it is urgent to apply better DNN in a faster way. Although, compared with GPU, FPGA has a higher energy efficiency ratio, and shorter development cycle and better flexibility than ASIC. However, FPGA is not a perfect hardware platform either for computational intelligence. This paper provides a survey of the latest acceleration work related to the familiar DNNs and proposes three new directions to break the bottleneck of the DNN implementation. So as to improve calculating speed and energy efficiency of edge devices, intelligent embedded approaches including model compression and optimized data movement of the entire system are most commonly used. With the gradual slowdown of Moore’s Law, the traditional Von Neumann Architecture generates a “Memory Wall” problem, resulting in more power-consuming. In-memory computation will be the right medicine in the post-Moore law era. More complete software/hardware co-design environment will direct researchers’ attention to explore deep learning algorithms and run the algorithm on the hardware level in a faster way. These new directions start a relatively new paradigm in computational intelligence, which have attracted substantial attention from the research community and demonstrated greater potential over traditional techniques.



中文翻译:

基于 FPGA 的计算智能的新范式来自调查 DNN 加速器的实施

随着人工智能、物联网、5G等技术的快速发展,出现了以图像识别、语音识别、自动驾驶、智能制造为代表的一批新兴智能应用。这些应用需要高效智能的处理系统来进行海量数据计算,因此迫切需要以更快的方式应用更好的 DNN。虽然与 GPU 相比,FPGA 比 ASIC 具有更高的能效比、更短的开发周期和更好的灵活性。然而,对于计算智能来说,FPGA 也不是一个完美的硬件平台。本文对与熟悉的 DNN 相关的最新加速工作进行了调查,并提出了三个新方向来打破 DNN 实现的瓶颈。为了提高边缘设备的计算速度和能源效率,最常用的智能嵌入式方法包括模型压缩和整个系统的优化数据移动。随着摩尔定律的逐渐放缓,传统的冯诺依曼架构产生了“内存墙”问题,导致功耗增加。内存计算将成为后摩尔定律时代的良药。更完善的软硬件协同设计环境将引导研究人员的注意力去探索深度学习算法,并以更快的方式在硬件层面上运行算法。这些新方向开创了计算智能领域相对较新的范式,引起了研究界的极大关注,并展示了比传统技术更大的潜力。

更新日期:2022-01-12
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