Embedded devices are omnipresent in our daily routine, from smartphones to home appliances, that run data and control-oriented applications. To maximize the energy-performance tradeoff, data and instruction-level parallelism are exploited by using superscalar and specific accelerators. However, as such devices have severe time-to-market, binary compatibility should be maintained to avoid recurrent engineering, which is not considered in current embedded processors. This work visited a set of embedded applications showing the need for concurrent ILP and DLP exploitation. For that, we propose a Hybrid Multi-Target Binary Translator (HMTBT) to transparently exploit ILP and DLP by using a CGRA and ARM NEON engine as targeted accelerators. Results show that HMTBT transparently achieves 24% performance improvements and 54% energy savings over an OoO superscalar processor coupled to an ARM NEON engine. The proposed approach improves performance and energy in 10%, 24% over decoupled binary translators using the same accelerator with the same ILP and DLP capabilities.

嵌入式设备在我们的日常生活中无处不在，从智能手机到家用电器，它们运行数据和面向控制的应用程序。为了最大限度地权衡能源性能，通过使用超标量和特定加速器来利用数据和指令级并行性。但是，由于此类设备的上市时间很长，因此应保持二进制兼容性以避免重复工程，这在当前的嵌入式处理器中并未考虑。这项工作访问了一组嵌入式应用程序，表明需要并发 ILP 和 DLP 开发。为此，我们提出了一种混合多目标二进制转换器 (HMTBT)，通过使用 CGRA 和 ARM NEON 引擎作为目标加速器来透明地利用 ILP 和 DLP。结果表明，与耦合到 ARM NEON 引擎的 OoO 超标量处理器相比，HMTBT 明显实现了 24% 的性能改进和 54% 的节能。与使用具有相同 ILP 和 DLP 功能的相同加速器的解耦二进制转换器相比，所提出的方法提高了 10% 和 24% 的性能和能量。