The simulation of Dynamic Random Access Memories (DRAMs) on system level requires highly accurate models due to their complex timing and power behavior. However, conventional cycle-accurate DRAM subsystem models often become a bottleneck for the overall simulation speed. A promising alternative are simulators based on Transaction Level Modeling, which can be fast and accurate at the same time. In this paper we present DRAMSys4.0, which is, to the best of our knowledge, the fastest and most extensive open-source cycle-accurate DRAM simulation framework. DRAMSys4.0 includes a novel software architecture that enables a fast adaption to different hardware controller implementations and new JEDEC standards. In addition, it already supports the latest standards DDR5 and LPDDR5. We explain how to apply optimization techniques for an increased simulation speed while maintaining full temporal accuracy. Furthermore, we demonstrate the simulator’s accuracy and analysis tools with two application examples. Finally, we provide a detailed investigation and comparison of the most prominent cycle-accurate open-source DRAM simulators with regard to their supported features, analysis capabilities and simulation speed.

由于复杂的时序和功率行为，系统级动态随机存取存储器 (DRAM) 的仿真需要高度精确的模型。然而，传统的周期精确 DRAM 子系统模型往往成为整体仿真速度的瓶颈。一个有前途的替代方案是基于事务级别建模的模拟器，它可以同时快速和准确。在本文中，我们介绍了 DRAMSys4.0，据我们所知，这是最快、最广泛的开源周期精确 DRAM 仿真框架。DRAMSys4.0 包括一个新颖的软件架构，能够快速适应不同的硬件控制器实施和新的 JEDEC 标准。此外，它已经支持最新的标准DDR5和LPDDR5。我们解释了如何应用优化技术来提高模拟速度，同时保持完整的时间精度。此外，我们通过两个应用示例演示了模拟器的准确性和分析工具。最后，我们对最突出的周期精确开源 DRAM 模拟器的支持特性、分析能力和模拟速度进行了详细调查和比较。