An error floor phenomenon, decoding performance, and throughput are three major concerns for LDPC decoders in NAND Flash applications. With a penalty method and an active iteration mechanism, we present a Unified Penalty Gradient Descent Bit Flipping (UP-GDBF) decoding algorithm, which not only possesses error-floor free property but also improves convergence speed in decoding performance. To fulfill the high-throughput requirement while maintaining reliable error correction capability, we propose an energy-based backtracking scheme to reduce 40% latency with a negligible 0.8% area overhead. Implemented in TSMC 16nm process, the proposed 4KB LDPC decoder can achieve a throughput of 19.3 Gbps with 0.120 mm2 area to satisfy ONFI 5.0 throughput requirement. Compared to existing approaches, our decoder architecture provides superior data rate and decoding performance in both 1KB and 4KB LDPC codes.

中文翻译：

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UP-GDBF：适用于 NAND 闪存应用的 19.3 Gbps 无误码 4KB LDPC 解码器

错误层现象、解码性能和吞吐量是 NAND 闪存应用中 LDPC 解码器的三个主要问题。通过惩罚方法和主动迭代机制，我们提出了统一惩罚梯度下降比特翻转（UP-GDBF）解码算法，该算法不仅具有无误码特性，而且提高了解码性能的收敛速度。为了在保持可靠纠错能力的同时满足高吞吐量要求，我们提出了一种基于能量的回溯方案，以减少 40% 的延迟，而面积开销可忽略不计 0.8%。所提出的 4KB LDPC 解码器采用台积电 16nm 工艺实现，在 0.120 mm2 的面积下可实现 19.3 Gbps 的吞吐量，以满足 ONFI 5.0 的吞吐量要求。与现有方法相比，