This paper provides a framework for analyzing the loop dynamics of the clock and data recovery (CDR) system of ADC-based PAM-4 receivers, which will assist in extending the timing recovery loop bandwidth. This paper formulates an accurate linear model of linear and signed Mueller–Muller phase detector for baud-rate clock recovery. Different equalization configurations of continuous-time linear equalizer (CTLE) and feed-forward equalizer (FFE) are evaluated from a phase detector performance perspective to enable high CDR loop bandwidth. The impact of loop latency on the timing recovery of ADC-based PAM-4 receivers is also analyzed and demonstrated using accurate behavioral simulations. The analysis and behavioral results show that, to achieve high CDR loop bandwidth with a good jitter tolerance, the phase detector gain to noise ratio should be maximized, and CDR loop latency should be minimized.

中文翻译：

---

PAM-4 Mueller-Muller时钟和数据恢复系统的环路动力学分析

本文提供了一个分析基于 ADC 的 PAM-4 接收器的时钟和数据恢复 (CDR) 系统的环路动态的框架，这将有助于扩展定时恢复环路带宽。本文制定了用于波特率时钟恢复的线性和有符号 Mueller-Muller 鉴相器的精确线性模型。从相位检测器性能的角度评估连续时间线性均衡器 (CTLE) 和前馈均衡器 (FFE) 的不同均衡配置，以实现高 CDR 环路带宽。循环延迟对基于 ADC 的 PAM-4 接收器的定时恢复的影响也通过准确的行为仿真进行了分析和演示。分析和行为结果表明，要实现具有良好抖动容限的高 CDR 环路带宽，