Rely/guarantee reasoning provides a compositional approach to reasoning about concurrent programs. However, such reasoning traditionally assumes a sequentially consistent memory model and hence is unsound on modern hardware in the presence of data races. In this article, we present a rely/guarantee-based approach for non-multicopy atomic weak memory models, i.e., where a thread’s stores are not simultaneously propagated to all other threads and hence are not observable by other threads at the same time. Such memory models include those of the earlier versions of the ARM processor as well as the POWER processor.

This article builds on our approach to compositional reasoning for multicopy atomic architectures, i.e., where a thread’s stores are simultaneously propagated to all other threads. In that context, an operational semantics can be based on thread-local instruction reordering. We exploit this to provide an efficient compositional proof technique in which weak memory behaviour can be shown to preserve rely/guarantee reasoning on a sequentially consistent memory model. To achieve this, we introduce a side-condition, reordering interference freedom on each thread, reducing the complexity of weak memory to checks over pairs of reorderable instructions.

In this article, we extend our approach to non-multicopy atomic weak memory models. We utilise the idea of reordering interference freedom between parallel components. This by itself would break compositionality but serves as a vehicle to derive a refined compatibility check between rely and guarantee conditions, which takes into account the effects of propagations of stores that are only partial, i.e., not covering all threads. All aspects of our approach have been encoded and proved sound in Isabelle/HOL.

依赖/保证推理提供了一种组合方法来推理并发程序。然而，这种推理传统上假设顺序一致的内存模型，因此在存在数据争用的现代硬件上是不合理的。在本文中，我们为非多复制原子弱内存模型提出了一种基于依赖/保证的方法，即线程的存储不会同时传播到所有其他线程，因此其他线程无法同时观察到。此类内存模型包括早期版本的 ARM 处理器以及 POWER 处理器的内存模型。

本文基于我们的多副本原子架构的组合推理方法，即线程的存储同时传播到所有其他线程。在该上下文中，操作语义可以基于线程本地指令重新排序。我们利用这一点来提供一种有效的组合证明技术，其中可以显示弱记忆行为以保留对顺序一致记忆模型的依赖/保证推理。为了实现这一目标，我们引入了一个附带条件，对每个线程上的干扰自由度进行重新排序，从而降低弱内存检查可重新排序指令对的复杂性。

在本文中，我们将我们的方法扩展到非多复制原子弱内存模型。我们利用重新排序并行组件之间的干扰自由度的想法。这本身会破坏组合性，但可以作为一种工具来导出依赖条件和保证条件之间的精细兼容性检查，该检查考虑了仅部分（即不覆盖所有线程）的存储传播的影响。我们方法的所有方面都已在 Isabelle/HOL 中进行了编码并证明是正确的。