Contemporary HPC hardware typically provides several levels of parallelism, e.g. multiple nodes, each having multiple cores (possibly with vectorization) and accelerators. Efficiently programming such systems usually requires skills in combining several low-level frameworks such as MPI, OpenMP, and CUDA. This overburdens programmers without substantial parallel programming skills. One way to overcome this problem and to abstract from details of parallel programming is to use algorithmic skeletons. In the present paper, we evaluate the multi-node, multi-CPU and multi-GPU implementation of the most essential skeletons Map, Reduce, and Zip. Our main contribution is a discussion of the efficiency of using multiple parallelization levels and the consideration of which fine-tune settings should be offered to the user.

现代 HPC 硬件通常提供多个级别的并行性，例如多个节点，每个节点具有多个内核（可能具有矢量化）和加速器。对此类系统进行高效编程通常需要结合多种低级框架（例如 MPI、OpenMP 和 CUDA）的技能。这会使没有大量并行编程技能的程序员负担过重。克服这个问题并从并行编程的细节中抽象出来的一种方法是使用算法框架。在本文中，我们评估了最重要的骨架 Map、Reduce 和 Zip 的多节点、多 CPU 和多 GPU 实现。我们的主要贡献是讨论了使用多个并行化级别的效率以及应该向用户提供哪些微调设置的考虑。