In this work, hafnium zirconium oxide (HZO)-based 100 × 100 nm² ferroelectric tunnel junction (FTJ) devices were implemented on a 300 mm wafer platform, using a baseline 65 nm CMOS process technology. FTJs consisting of TiN/HZO/TiN were integrated in between metal 1 (M1) and via 1 (V1) layers. Cross-sectional transmission electron microscopy and energy dispersive x-ray spectroscopy analysis confirmed the targeted thickness and composition of the FTJ film stack, while grazing incidence, in-plane x-ray diffraction analysis demonstrated the presence of orthorhombic phase Pca2₁ responsible for ferroelectric polarization observed in HZO films. Current measurement, as a function of voltage for both up- and down-polarization states, yielded a tunneling electroresistance (TER) ratio of 2.28. The device TER ratio and endurance behavior were further optimized by insertion of thin Al₂O₃ tunnel barrier layer between the bottom electrode (TiN) and ferroelectric switching layer (HZO) by tuning the band offset between HZO and TiN, facilitating on-state tunneling conduction and creating an additional barrier layer in off-state current conduction path. Investigation of current transport mechanism showed that the current in these FTJ devices is dominated by direct tunneling at low electric field (E < 0.4 MV/cm) and by Fowler–Nordheim (F–N) tunneling at high electric field (E > 0.4 MV/cm). The modified FTJ device stack (TiN/Al₂O₃/HZO/TiN) demonstrated an enhanced TER ratio of ∼5 (2.2× improvement) and endurance up to 10⁶ switching cycles. Write voltage and pulse width dependent trade-off characteristics between TER ratio and maximum endurance cycles (N_c) were established that enabled optimal balance of FTJ switching metrics. The FTJ memory cells also showed multi-level-cell characteristics, i.e., 2 bits/cell storage capability. Based on full 300 mm wafer statistics, a switching yield of >80% was achieved for fabricated FTJ devices demonstrating robustness of fabrication and programming approach used for FTJ performance optimization. The realization of CMOS-compatible nanoscale FTJ devices on 300 mm wafer platform demonstrates the promising potential of high-volume large-scale industrial implementation of FTJ devices for various nonvolatile memory applications.

中文翻译：

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在 300 mm 晶圆平台上实现高性能和高产量的纳米级氧化铪锆基铁电隧道结器件

^{在这项工作中，基于 100 × 100 nm 2}铁电隧道结 (FTJ)的铪锆氧化物 ( FTJ) 器件使用基准 65 nm CMOS 工艺技术在 300 mm 晶圆平台上实现。由 TiN/HZO/TiN 组成的 FTJ 集成在金属 1 (M1) 和通孔 1 (V1) 层之间。横截面透射电子显微镜和能量色散 X 射线光谱分析证实了 FTJ 薄膜堆叠的目标厚度和组成，而掠入射、面内 X 射线衍射分析表明存在正交相 Pca2 ₁负责在 HZO 薄膜中观察到的铁电极化。电流测量作为上极化和下极化状态电压的函数，产生了 2.28 的隧道电阻 (TER) 比。通过调整 HZO 和 TiN 之间的能带偏移，在底部电极 (TiN) 和铁电开关层 (HZO) 之间插入薄的 Al ₂ O ₃隧道势垒层，进一步优化了器件的 TER 比和耐久性行为，促进了导通态隧道效应传导并在断态电流传导路径中创建额外的阻挡层。对电流传输机制的研究表明，这些 FTJ 器件中的电流主要由低电场下的直接隧穿决定（E < 0.4 MV/cm) 和 Fowler–Nordheim (F–N) 在高电场 ( E  > 0.4 MV/cm) 下隧道效应。修改后的 FTJ 器件堆栈（TiN/Al ₂ O ₃ /HZO/TiN）表现出增强的 TER 比率为 ∼5（2.2 倍改进）和高达 10 ^{6 个}开关周期的耐久性。TER 比率和最大耐久性循环之间的写入电压和脉冲宽度相关权衡特性 (N _c) 的建立可实现 FTJ 转换指标的最佳平衡。FTJ 存储单元还显示出多级单元特性，即 2 位/单元存储能力。基于完整的 300 毫米晶圆统计数据，制造的 FTJ 器件实现了 >80% 的开关良率，证明了用于 FTJ 性能优化的制造和编程方法的稳健性。在 300 毫米晶圆平台上实现 CMOS 兼容的纳米级 FTJ 器件展示了 FTJ 器件在各种非易失性存储器应用中大批量大规模工业实施的巨大潜力。