This paper presents an electrocardiogram acquisition analog front-end (AFE) with a noise tolerant heartbeat (HB) detector. Source degradation and transconductance bootstrap techniques are incorporated into the AFE to reduce the 1/f noise of the amplifier. Furthermore, the chopper modulation, DC-servo loop (DSL) and pre-charge technology are combined to reduce interference from the environment. A mixed-signal implementation of HB detector with the symmetric-comparison loop is proposed to reduce the power consumption and area, which also suppresses motion artifact interference by adaptive thresholds. Implemented in $0.18 ~\mu \text{m}$ CMOS process, the circuit only occupies an area of $0.122 mm^{2}$ and consumes $0.62 ~\mu \text{W}$ at a 1.2-V supply, of which AFE and HB detector consume 507 nW and 110 nW, respectively. Simulation results show that the gain and the CMRR of AFE range from 30–45 dB and 65–105 dB, respectively. The input-referred noise is 670 nVrms with a mid-band gain of 42 dB and a bandwidth ranging from 0.5 Hz to 1 kHz.

中文翻译：

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具有抗噪心跳检测器的 672nW、670nVrms ECG 采集 AFE

本文介绍了一种带有噪声容限心跳 (HB) 检测器的心电图采集模拟前端 (AFE)。源衰减和跨导自举技术被纳入 AFE 以降低放大器的 1/f 噪声。此外，斩波调制、直流伺服环路 (DSL) 和预充电技术相结合，以减少来自环境的干扰。提出了一种具有对称比较环路的 HB 检测器的混合信号实现，以降低功耗和面积，同时通过自适应阈值抑制运动伪影干扰。实施于 $0.18 ~\mu\text{m}$CMOS工艺，电路仅占面积 $0.122 毫米^{2}$并消耗 $0.62 ~\mu\text{W}$在 1.2 V 电源下，AFE 和 HB 检测器分别消耗 507 nW 和 110 nW。仿真结果表明，AFE 的增益和 CMRR 范围分别为 30–45 dB 和 65–105 dB。输入参考噪声为 670 nVrms，中频带增益为 42 dB，带宽范围为 0.5 Hz 至 1 kHz。