Packet-processing data planes have been continuously enhanced in performance over the last few years to the point that, nowadays, they are increasingly implemented in hardware (i.e., in SmartNICs and programmable switches). However, little attention is given to the slow path residing between the data plane and the control plane, as it is not typically considered performance-critical.

In this paper, we show that the slow path is set to become a new key bottleneck in Software-Defined Networks (SDNs). This is due to the growth in physical network bandwidth (200 Gbps is becoming common in data centers) and topological complexity (e.g., virtual switches now span hundreds of physical machines). We present our vision of a new Domain Specific Accelerator (DSA) for the slow path at the end host that sits between the hardware-offloaded data plane and the logically-centralized control plane. We discuss open problems in this domain and call on the networking community to creatively address this emerging issue.

在过去几年中，数据包处理数据平面的性能不断提高，以至于如今它们越来越多地在硬件中实现（即在 SmartNIC 和可编程交换机中）。然而，很少有人关注驻留在数据平面和控制平面之间的慢速路径，因为它通常不被认为是性能关键的。

在本文中，我们表明慢速路径将成为软件定义网络 (SDN) 中新的关键瓶颈。这是由于物理网络带宽（200 Gbps 在数据中心变得普遍）和拓扑复杂性（例如，虚拟交换机现在跨越数百台物理机器）的增长。我们提出了一种新的域特定加速器 (DSA) 的愿景，用于位于硬件卸载数据平面和逻辑集中控制平面之间的终端主机的慢速路径。我们讨论了这个领域中的开放问题，并呼吁网络社区创造性地解决这个新出现的问题。