In this paper, a negative capacitance (NC) effect in series with normal oxide capacitance is first time introduced to design negative capacitance charge plasma-based junction less vertical TFET structure (NC-CP-JL-VTFET). The introduced negative capacitance enhances the overall gate capacitance and hence gate capacitive coupling and thus renders high current capabilities with reduced sub-threshold slope and threshold voltage. With the use of negative capacitance along with oxide capacitance, it has been seen that the same drain current is achieved at lower gate voltage as compared to without use of negative capacitance and since the voltage scaling is done considerably, the dynamic power dissipation in circuit application can be reduced significantly. To generate the negative capacitance during the device operation; ferroelectric material $P$(VDF-TrFE) poly(vinylidene fluoride-trifluoro ethylene) is used in stack with SiO₂ gate oxide. Various performance parameters of the designed structure such as electron–hole concentration in the tunneling junction, electric field, surface potential, electron–hole quasi-Fermi variation, and drain current variation are investigated and compared with the results of without considering the ferroelectric material in the gate oxide. The variation of the ferroelectric thickness on the device performance is also investigated. The investigation exhibits significant improvement in the drain current and in the other parameters as well. These improvements are seen because of higher capacitive coupling and these effects are further responsible for more energy band bending which in turn govern high electron tunneling. Due to the existence of negative capacitance, the peak value of the electric field gets doubled while the surface potential increases 44% from the normal structure.

本文首次引入与普通氧化物电容串联的负电容（NC）效应来设计负电容电荷等离子体基无结垂直TFET结构（NC-CP-JL-VTFET）。引入的负电容增强了总体栅极电容，从而增强了栅极电容耦合，从而提供了高电流能力，同时降低了亚阈值斜率和阈值电压。通过使用负电容和氧化物电容，可以看出，与不使用负电容相比，可以在较低的栅极电压下实现相同的漏极电流，并且由于电压缩放相当大，因此可以显着降低电路应用中的动态功耗。器件工作时产生负电容；铁电材料$磷$_{(VDF-TrFE)聚偏二氟乙烯-三氟乙烯与SiO 2}叠层使用栅极氧化物。研究了设计结构的各种性能参数，如隧道结中的电子空穴浓度、电场、表面电势、电子空穴准费米变化和漏极电流变化，并与不考虑栅极氧化物中铁电材料的结果进行比较。还研究了铁电厚度的变化对器件性能的影响。研究表明漏极电流和其他参数也有显着改善。这些改进是由于更高的电容耦合而看到的，并且这些效应进一步导致了更多的能带弯曲，而这反过来又控制了高电子隧道效应。由于负电容的存在，