In this paper, it is proposed a jitter analysis methodology, targeting on the optimization of a phase interpolator (PI) based clock and data recovery circuit (CDR). The methodology is applied for the optimized design of an 8-bit dual-loop CDR, designed with the CMOS TSMC 65 nm process node. The CDR is based on an extended, in terms of phase resolution, version, with a novel PI topology proposed in this work. The proposed CDR loop has a minimum frequency offset tracking ability equal to 500ppm at 5.83 Gbps, and so is suitable for adoption either in mesochronous or plesiochronous High Speed Serial Interface (HSSI) receivers. It consumes 14.2 mW with 1 V supply voltage and is able to achieve better than 10 ⁻¹⁰ Bit Error Rate (BER) performance. The CDR loop performance verification has been realized through the AMS simulator of Analog Design Environment of Cadence, by co-simulations of the transistor level CDR circuit with the Verilog-AMS based jitter generator.

中文翻译：

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具有抖动优化的基于相位插值器的时钟和数据恢复

本文提出了一种抖动分析方法，针对基于相位插值器（PI）的时钟和数据恢复电路（CDR）的优化。该方法适用于采用 CMOS TSMC 65 nm 工艺节点设计的 8 位双环路 CDR 的优化设计。CDR 基于相位分辨率方面的扩展版本，并采用本工作中提出的新颖 PI 拓扑。所提出的 CDR 环路在 5.83 Gbps 时具有等于 500ppm 的最小频率偏移跟踪能力，因此适合在中同步或准同步高速串行接口 (HSSI) 接收器中采用。电源电压为 1 V 时，功耗为 14.2 mW，能够实现优于 10 ⁻¹⁰误码率 (BER) 性能。通过Cadence模拟设计环境的AMS仿真器，对晶体管级CDR电路与基于Verilog-AMS的抖动发生器进行联合仿真，实现了CDR环路性能验证。