In this work the electrical behaviour of CMOS winner take all (WTA) cells is exploited to create a novel topology for physical unclonable functions (PUF) using current mirrors. The basic cell is based on low cascode current mirrors and high-gain Sekkerkiran WTA cells. These cells are capable to select a winner neuron according to manufacture process variations. Post-layout validation of the cell was performed using Cadence Virtuoso tools with a 65nm UMC technology. The PUF energy consumption is 5.670pJ/b with native bit instability of 2.294% among 1024 readings considering temperature variations. The PUF performance is quantified with uniqueness, uniformity and reliability metrics yielding results of 49.614%, 49.662% and 97.706% respectively among 1000 considered instances. An average inter-HD=49.837%, and intra-HD=1.570% are obtained assuming temperature variation from (-20C \(\sim\) 120C) and 300mV of supply voltage fluctuation, the key generation latency is 73ns (8b), while the true randomness of keys is proved by NIST and autocorrelation function (ACF) tests.

在这项工作中，利用 CMOS 胜者通吃 (WTA) 单元的电气行为，利用电流镜为物理不可克隆功能 (PUF) 创建一种新颖的拓扑。基本单元基于低共源共栅电流镜和高增益 Sekkerkiran WTA 单元。这些细胞能够根据制造过程的变化选择获胜的神经元。使用采用 65nm UMC 技术的 Cadence Virtuoso 工具对单元进行布局后验证。考虑到温度变化，PUF 能耗为 5.670pJ/b，在 1024 个读数中，本机位不稳定性为 2.294%。PUF 性能通过唯一性、均匀性和可靠性指标进行量化，在 1000 个考虑的实例中分别产生 49.614%、49.662% 和 97.706% 的结果。平均帧间HD=49.837%，帧内HD=1。在\(\sim\) 120C）和300mV的电源电压波动下，密钥生成延迟为73ns（8b），而密钥的真正随机性经过NIST和自相关函数（ACF）测试证明。