In practical quantum error correction implementations, the measurement of syndrome information is an unreliable step—typically modeled as a binary measurement outcome flipped with some probability. However, the measured syndrome is in fact a discretized value of the continuous voltage or current values obtained in the physical implementation of the syndrome extraction. In this paper, we use this “soft” or analog information to benefit iterative decoders for decoding quantum low-density parity-check (QLDPC) codes. Syndrome-based iterative belief propagation decoders are modified to utilize the soft syndrome to correct both data and syndrome errors simultaneously. We demonstrate the advantages of the proposed scheme not only in terms of comparison of thresholds and logical error rates for quasi-cyclic lifted-product QLDPC code families but also with faster convergence of iterative decoders. Additionally, we derive hardware (FPGA) architectures of these soft syndrome decoders and obtain similar performance in terms of error correction to the ideal models even with reduced precision in the soft information. The total latency of the hardware architectures is about 600 ns (for the QLDPC codes considered) in a 20 nm CMOS process FPGA device, and the area overhead is almost constant—less than 50% compared to min-sum decoders with noisy syndromes.

中文翻译：

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量子LDPC码的软征候迭代解码和硬件架构

在实际的量子纠错实现中，校正子信息的测量是一个不可靠的步骤——通常建模为以某种概率翻转的二进制测量结果。然而，测量的校正子实际上是在校正子提取的物理实现中获得的连续电压或电流值的离散化值。在本文中，我们使用这种“软”或模拟信息来使迭代解码器解码量子低密度奇偶校验（QLDPC）码。基于校正子的迭代置信传播解码器被修改为利用软校正子同时纠正数据和校正子错误。我们不仅在准循环提升积 QLDPC 码族的阈值和逻辑错误率比较方面证明了所提出方案的优点，而且在迭代解码器的更快收敛方面也证明了该方案的优点。此外，我们推导了这些软校正子解码器的硬件（FPGA）架构，并在纠错方面获得了与理想模型相似的性能，即使软信息的精度降低了。在 20 nm CMOS 工艺 FPGA 器件中，硬件架构的总延迟约为 600 ns（对于所考虑的 QLDPC 代码），并且面积开销几乎恒定，与具有噪声综合症的最小和解码器相比不到 50%。