Energy-efficient rapid single flux quantum (ERSFQ) devices have unique energy advantages with a power consumption of less than 0.001fJ per single-bit switch, even considering the energy required for the refrigeration system, achieving ultra-low energy consumption of sub-fJ/bit. Combined with its typical operating frequency in the tens of GHz range, ERSFQ circuits have the potential to realize computing chips with extremely high computational power and energy efficiency, making them highly promising for applications in the post-Moore era. However, the performance improvement of ERSFQ circuits faces two challenges. One is how to reduce the size of their feeding Josephson transmission line (FJTL), which is required to stabilize the voltage bias of the ERSFQ circuits. The second challenge is how to improve their bias margin. The measured bias margin of ERSFQ circuits is relatively smaller than for Rapid Single Flux Quantum (RSFQ) circuits. This study investigates the current compensation mechanism of the FJTL and derives a formula for the compensating current ΔI in the main logic circuit by each pulse input to the FJTL. Based on the formula, a method is proposed to enhance the bias margin of ERSFQ circuits while reducing the size of FJTL by applying feeding pulses into the FJTL. We applied this method to an 8-bit ERSFQ shift register (SR), where the size of its FJTL is 4 JTLs (each JTL consists of 2 Josephson junctions). The measurement demonstrated an improvement of the bias margin from [84 %, 104 %] to [38 %, 104 %], confirming the feasibility of the proposed method. Furthermore, by comparing the measurement results of an 8-bit ERSFQ SR, where the size of its FJTL is 6 JTLs, it is demonstrated that applying this method can also reduce the size of the FJTL while maintaining a large margin.

高效节能的快速单通量量子（ERSFQ）器件具有独特的能源优势，每一位开关的功耗低于0.001fJ，即使考虑制冷系统所需的能量，实现亚fJ的超低能耗/少量。结合其在数十GHz范围内的典型工作频率，ERSFQ电路有潜力实现具有极高计算能力和能效的计算芯片，使其在后摩尔时代的应用前景广阔。然而，ERSFQ电路的性能提升面临两个挑战。一是如何减小馈电约瑟夫森传输线（FJTL）的尺寸，这是稳定 ERSFQ 电路的电压偏置所必需的。第二个挑战是如何提高其偏差裕度。ERSFQ 电路的测量偏置裕度相对小于快速单通量量子 (RSFQ) 电路。本研究研究了FJTL的电流补偿机制，并推导了输入到FJTL的每个脉冲在主逻辑电路中的补偿电流ΔI的公式。基于该公式，提出了一种通过向 FJTL 施加馈送脉冲来增强 ERSFQ 电路的偏置裕度，同时减小 FJTL 尺寸的方法。我们将此方法应用于 8 位 ERSFQ 移位寄存器（SR），其 FJTL 的大小为 4 个 JTL（每个 JTL 由 2 个约瑟夫森结组成）。测量结果表明，偏差裕度从[84%, 104%] 提高到[38%, 104%]，证实了该方法的可行性。此外，通过比较8位ERSFQ SR（其FJTL的大小为6个JTL）的测量结果，证明应用该方法还可以在保持较大余量的同时减小FJTL的大小。