Agile hardware development methodology has been widely adopted over the past decade. Despite the research progress, the industry still doubts its applicability, especially for the functional verification of complicated processor chips. Functional verification commonly employs a simulation-based method of co-simulating the design under test with a reference model and checking the consistency of their outcomes given the same input stimuli. We observe limited collaboration and information exchange through the design and verification processes, dramatically leading to inefficiencies when applying the conventional functional verification workflow to agile development. In this paper, we propose workflow integration with collaborative task delegation and dynamic information exchange as the design principles to effectively address the challenges on functional verification under the agile development model. Based on workflow integration, we enhance the functional verification workflows with a series of novel methodologies and toolchains. The diff-rule based agile verification methodology (DRAV) reduces the overhead of building reference models with runtime execution information from designs under test. We present the RISC-V implementation for DRAV, DiffTest, which adopts information probes to extract internal design behaviors for co-simulation and debugging. It further integrates two plugins, namely XFUZZ for effective test generation guided by design coverage metrics and LightSSS for efficient fault analysis triggered by co-simulation mismatches. We present the integrated workflows for agile hardware development and demonstrate their effectiveness in designing and verifying RISC-V processors with 33 functional bugs found in NutShell. We also illustrate the efficiency of the proposed toolchains with a case study on a functional bug in the L2 cache of XiangShan.

敏捷硬件开发方法在过去十年中已被广泛采用。尽管研究取得了进展，但业界仍然对其适用性表示怀疑，尤其是对于复杂处理器芯片的功能验证。功能验证通常采用基于仿真的方法，将被测设计与参考模型进行联合仿真，并在给定相同输入刺激的情况下检查其结果的一致性。我们观察到，设计和验证过程中的协作和信息交换有限，这极大地导致了将传统功能验证工作流程应用于敏捷开发时效率低下。在本文中，我们提出以协作任务委托和动态信息交换的工作流集成为设计原则，以有效解决敏捷开发模式下功能验证的挑战。基于工作流集成，我们通过一系列新颖的方法和工具链增强了功能验证工作流程。基于 diff 规则的敏捷验证方法 (DRAV) 减少了使用被测设计的运行时执行信息构建参考模型的开销。我们提出了 DRAV、DiffTest 的 RISC-V 实现，它采用信息探针来提取内部设计行为以进行协同仿真和调试。它还集成了两个插件，即 XFUZZ（用于以设计覆盖率指标为指导的有效测试生成）和 LightSSS（用于由协同仿真不匹配触发的高效故障分析）。我们提出了敏捷硬件开发的集成工作流程，并展示了它们在设计和验证 RISC-V 处理器时的有效性，以及在Nut S hell中发现的 33 个功能错误。我们还通过对湘山二级缓存功能错误的案例研究来说明所提出的工具链的效率。