The increasing demand for high performance and energy efficiency in Artificial Neural Networks (ANNs) accelerators has driven a wide range of application-specific integrated circuits (ASICs). Besides, the rapid deployment of low-power IoT devices requires highly efficient computing, which as a result urges the need to explore low-power hardware implementations in different domains. This paper proposes a spatially unrolled time-domain accelerator that uses an ultra-low-power digital-to-time converter (DTC) while occupying an active area of 0.201 mm2. The proposed DTC is implemented using a Laddered, Inverter (LI) circuit, which consumes 3 $\times $ less power than the conventional inverter-based DTC and provides reliable performance across different process corners, supply voltages, and temperature variations. Post-synthesis results in 65nm CMOS show that the proposed core achieves a superior energy efficiency of 116 TOPS/W, a throughput of 4 GOPS, and an area efficiency of 20 GOPS/mm2. The proposed core improves energy efficiency by 2.4 - 47 $\times $ compared to prior time-domain accelerators.

中文翻译：

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116 TOPS/W 空间展开时域加速器，利用梯级逆变器 DTC 在 65 nm 中实现节能边缘计算

对人工神经网络 (ANN) 加速器高性能和高能效的需求不断增长，推动了各种专用集成电路 (ASIC) 的发展。此外，低功耗物联网设备的快速部署需要高效的计算，因此需要探索不同领域的低功耗硬件实现。本文提出了一种空间展开的时域加速器，它使用超低功耗数字时间转换器（DTC），同时占用 0.201 mm2 的有效面积。建议的 DTC 使用梯形逆变器 (LI) 电路实现，该电路消耗 3 $\次$比传统的基于逆变器的 DTC 功耗更低，并且在不同的工艺角、电源电压和温度变化下提供可靠的性能。65nm CMOS 的后合成结果表明，所提出的内核实现了 116 TOPS/W 的卓越能效、4 GOPS 的吞吐量和 20 GOPS/mm2 的面积效率。拟议的核心将能源效率提高了 2.4 - 47 $\次$与之前的时域加速器相比。