Several works report on overcoming the challenge of complex general-purpose signal processing algorithms that result in quick utilization of chip area resources (like FPGA in implementing system on chip or network on chip). However, with the advent of machine learning and deep learning algorithms, reducing this complexity and immense use of resources is a challenging task that can improve the system’s performance in real time. One of the approaches is algorithm optimization, which consumes fewer resources and produces an equivalent performance. This approach may likely be accepted in less-sensitive applications, like voice or video processing. Recently, an optimized algorithm of correlation-less Wiener–Hopf-based adaptive channel equalizer is reported, in which the overall complexity of the system is reduced by employing a more compact way of weight optimization. This paper is the continuation of that work that reports the modification in the Steepest-Descent-based adaptive channel equalizer algorithm by keeping the autocorrelation matrix out of the algorithm. The proposed design is simulated and tested at equivalent spectral performance and produces comparable performance with fewer chip resources when translated on FPGA. The proposed design supports that algorithm-level optimization may be accepted extensively for the optimal hardware-based design of DSP systems.

一些工作报告了如何克服复杂通用信号处理算法的挑战，从而快速利用芯片区域资源（例如实现片上系统或片上网络的 FPGA）。然而，随着机器学习和深度学习算法的出现，降低这种复杂性和大量资源的使用是一项具有挑战性的任务，可以实时提高系统的性能。其中一种方法是算法优化，它消耗更少的资源并产生相同的性能。这种方法可能会在不太敏感的应用中被接受，例如语音或视频处理。最近，报道了一种基于无相关维纳-霍普夫的自适应信道均衡器的优化算法，其中通过采用更紧凑的权重优化方式来降低系统的整体复杂度。本文是该工作的延续，报告了通过将自相关矩阵排除在算法之外，对基于最速下降的自适应信道均衡器算法进行的修改。所提出的设计在等效频谱性能下进行了仿真和测试，并在 FPGA 上转换时以更少的芯片资源产生了可比的性能。所提出的设计支持算法级优化可以被广泛接受，用于 DSP 系统的基于硬件的最佳设计。