This paper proposes a hybrid phase detector for use in multilevel timing recovery systems. The proposed approach suppresses errant zero-crossings associated with multilevel baud rate phase detectors and ensures maximum signal swing in lock, with minimal hardware and power overhead. Analysis and simulation results in a 28nm CMOS process are used to explore the functionality of proposed phase detector and demonstrate its effectiveness in achieving superior performance to the conventional approach.Clock and data recovery (CDR) loop simulations show that the proposed phase detector enables $1.36\times $ increase in vertical eye margin while maintaining similar steady-state RMS jitter and compared to the conventional approach. The simulations also show effective suppression of unwanted phase detector zero-crossing, while achieving comparable acquisition bandwidth to the conventional approach.

中文翻译：

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用于波特率多级时钟和数据恢复的混合定时错误检测器

本文提出了一种用于多级定时恢复系统的混合相位检测器。所提出的方法可抑制与多级波特率相位检测器相关的错误过零，并确保最大信号摆幅锁定，同时具有最小的硬件和功率开销。28nm CMOS 工艺中的分析和仿真结果用于探索所提出的相位检测器的功能，并证明其在实现优于传统方法的性能方面的有效性。时钟和数据恢复 (CDR) 环路仿真表明，所提出的相位检测器能够实现 $1.36\次$与传统方法相比，垂直眼图余量增加，同时保持相似的稳态 RMS 抖动。仿真还显示了对不需要的相位检测器过零的有效抑制，同时实现了与传统方法相当的采集带宽。