In this paper, a new high speed two-stage charge pump is designed for phase-locked loop (PLL) application. In the proposed circuit, switch-based charge pump acts as the primary charge pump for glitch-free output, in addition to that MOS current mode logic (MCML) based faster current driving charge pump acts as the secondary charge pump. It will used to achieve the PLL locking condition quickly. MCML circuits minimize delay and perform the fast operation, hence it can be used in high frequency applications. The proposed circuit achieves very low power of 13.19 μW with a minimum delay of 16.71 ps at 45 nm CMOS technology with a 1 V power supply in different process corners. The output noise as very low as − 232.7 dB and phase noise as − 247.2 dBc/Hz at 10 GHz frequency. The swing voltage ranges from 0 to 980 mV. Monte-Carlo simulations with 200 samples are analysed to verify the results. Finally, process voltage and temperature (PVT) analysis are performed to validate the stability of the proposed design. The simulated results shows that the proposed circuit is more stable for high-frequency PLL applications and is highly tolerant with PVT variations.

本文设计了一种新型高速两级电荷泵，用于锁相环（PLL）应用。在所提出的电路中，基于开关的电荷泵充当主电荷泵以实现无毛刺输出，此外基于 MOS 电流模式逻辑 (MCML) 的更快电流驱动电荷泵充当辅助电荷泵。它将用于快速实现PLL锁定条件。MCML电路最大限度地减少延迟并执行快速操作，因此它可以用于高频应用。所提出的电路在不同工艺角采用 1 V 电源的 45 nm CMOS 技术实现了 13.19 μW 的极低功耗和 16.71 ps 的最小延迟。在 10 GHz 频率下，输出噪声极低至 − 232.7 dB，相位噪声极低至 − 247.2 dBc/Hz。摆幅电压范围为 0 至 980 mV。对 200 个样本进行蒙特卡罗模拟分析以验证结果。最后，进行工艺电压和温度（PVT）分析以验证所提出设计的稳定性。仿真结果表明，所提出的电路对于高频 PLL 应用更加稳定，并且对 PVT 变化具有高度的容忍度。