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A low power arithmetic unit driven motion estimation and intra prediction accelerators with adaptive Golomb–Rice entropy encoder for H.264 encoders on FPGA
Analog Integrated Circuits and Signal Processing ( IF 1.4 ) Pub Date : 2024-01-05 , DOI: 10.1007/s10470-023-02222-3
L. Vigneash , H. Azath , Lakshmi R. Nair , Kamalraj Subramaniam

In the recent era, the utilization of the H.264 encoder has been increasing due to its outstanding performance in video compression. However, compressing video with reduced power is still a challenging issue faced by H.264 encoders. Thus, the proposed study intends to minimize the power consumption of H.264 encoders on FPGA by optimizing the basic components of H.264, thereby enhancing performance. For this purpose, the elements like Motion Estimation, intra-prediction, transform unit and entropy encoder are optimized through the effective schemes introduced in the proposed work. Initially, the Motion Estimation unit can be alternated by optimizing the fundamental components of Block Matching Algorithms. To design the Block Matching Algorithms, the proposed study introduces low-power arithmetic units like an add-one circuit-based Carry SeLect Adder and Sum of Absolute Difference. With the help of these methods, the Block Matching Algorithms has designed, and the Motion Estimation Unit can be effectively optimized. Then, by adopting a comparator-less reusing method, the intra-prediction unit is optimized. Next, the transform unit is optimized by proposing a Steerable Discrete Cosine Transform and finally, the entropy encoders are optimized by combining Golomb and Rice entropy encoders. The proposed study uses the schemes above to improve the efficiency of H.264 encoders on FPGA. The experimental analysis in the proposed study is done using Xilinx software. The simulation results show that the proposed work obtained higher power, LUTs, delay, PSNR, frequency and MSE than other competing methods.



中文翻译:

低功耗算术单元驱动的运动估计和帧内预测加速器,具有适用于 FPGA 上的 H.264 编码器的自适应 Golomb-Rice 熵编码器

近年来,由于 H.264 编码器在视频压缩方面的出色性能,其利用率不断增加。然而,以降低的功率压缩视频仍然是 H.264 编码器面临的一个具有挑战性的问题。因此,本研究旨在通过优化H.264的基本组件来最小化FPGA上H.264编码器的功耗,从而提高性能。为此,通过所提出的工作中引入的有效方案对运动估计、帧内预测、变换单元和熵编码器等元素进行了优化。最初,可以通过优化块匹配算法的基本组件来替换运动估计单元。为了设计块匹配算法,本研究引入了低功耗算术单元,例如基于加一电路的进位选择加法器和绝对差和。借助这些方法,设计了块匹配算法,并且可以有效地优化运动估计单元。然后,通过采用无比较器重用方法,对帧内预测单元进行优化。接下来,通过提出可操纵离散余弦变换来优化变换单元,最后,通过结合 Golomb 和 Rice 熵编码器来优化熵编码器。本研究使用上述方案来提高 FPGA 上 H.264 编码器的效率。本研究中的实验分析是使用 Xilinx 软件完成的。仿真结果表明,与其他竞争方法相比,所提出的工作获得了更高的功率、LUT、延迟、PSNR、频率和 MSE。

更新日期:2024-01-05
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