Low-dimensional nanomaterials provide promising material platforms for aggressively scaled transistor technologies. We assess the performance potential of transistors based on an array of Tellurium nanowires (TNWs), by parameterizing a machine-learning (ML) tight-binding model with quantum transport device simulations. It has been shown that a transistor based on a parallel array of carbon nanotubes (CNTs) can have excellent on-state performance, but the small bandgap limits the transistor scalability and off-state performance. Our results indicate that compared to the CNT array FETs, the TNW array FETs have significantly suppressed ambipolar transport and improved subthreshold characteristics. The TNW array FET has the potential to achieve a near-ideal subthreshold swing (SS) close to 60 mV/dec, a very large on–off ratio (>10⁹), and low source-drain leakage current at a 10 nm-scale channel length, due to its excellent gate electrostatics with a gate-all-around (GAA) structure, larger band gap and reduced quantum–mechanical tunneling. The TNW array FET also shows excellent scalability with a SS below 100 mV/dec when the channel length is further scaled down to 5 nm. Its larger bandgap and heavier effective mass significantly reduce quantum tunneling. This mechanism contributes to improved subthreshold and lower leakage but also highlights the need to develop low Schottky barrier contacts for TNWs.

低维纳米材料为大规模晶体管技术提供了有前景的材料平台。我们通过量子传输器件模拟参数化机器学习 (ML) 紧束缚模型，评估基于碲纳米线 (TNW) 阵列的晶体管的性能潜力。事实证明，基于碳纳米管（CNT）平行阵列的晶体管可以具有优异的通态性能，但小带隙限制了晶体管的可扩展性和断态性能。我们的结果表明，与 CNT 阵列 FET 相比，TNW 阵列 FET 显着抑制了双极输运并改善了亚阈值特性。TNW 阵列 FET 有潜力实现接近 60 mV/dec 的近乎理想的亚阈值摆幅 (SS)、非常大的开关比 (>10 ⁹ ) 以及 10 nm 时的低源漏漏电流。规模沟道长度，由于其优异的栅极静电和环栅（GAA）结构，更大的带隙和减少的量子力学隧道效应。当沟道长度进一步缩小至 5 nm 时，TNW 阵列 FET 还表现出出色的可扩展性，SS 低于 100 mV/dec。其较大的带隙和较重的有效质量显着减少了量子隧道效应。这种机制有助于改善亚阈值和降低泄漏，但也凸显了开发用于 TNW 的低肖特基势垒接触的必要性。