Reducing trigger voltage has always been a research hotspot in low-voltage electrostatic discharge (ESD) protection applications for integrated circuit. Thus, a novel low trigger voltage low leakage silicon-controlled rectifier (LTVLLSCR) for low-voltage ESD protection has been proposed. The proposed device uses a PMOS connected with the SCR to reduce the trigger voltage and the PMOS gate can be applied with the supply voltage to further reduce the trigger voltage and the leakage current. The operating principle and the physical mechanism of the proposed device were discussed by the Human Body Model simulation. The ESD characteristics of the proposed device were verified in 55 nm CMOS process. The experimental results demonstrate that the trigger voltage of the proposed device can reach a minimum of 2.86 V with an external bias, and the leakage current at 25 °C is about 1 nA which can be reduced by 13% with an external bias. With lower trigger voltage, lower leakage, smaller ESD design window and good ESD robustness, the LTVLLSCR is very suitable for 1 V low voltage applications.

中文翻译：

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一种用于低压 ESD 保护的新型低触发电压低漏电 SCR

降低触发电压一直是集成电路低压静电放电（ESD）保护应用的研究热点。因此，提出了一种用于低压ESD保护的新型低触发电压低泄漏硅控整流器（LTVLLSCR）。所提出的器件使用与SCR连接的PMOS来降低触发电压，并且PMOS栅极可以施加电源电压以进一步降低触发电压和漏电流。通过人体模型模拟讨论了该装置的工作原理和物理机制。所提出器件的 ESD 特性在 55 nm CMOS 工艺中得到验证。实验结果表明，在外部偏置下，该器件的触发电压最低可达2.86 V，25°C时的漏电流约为1 nA，在外部偏置下可降低13%。 LTVLLSCR 具有更低的触发电压、更低的泄漏、更小的 ESD 设计窗口和良好的 ESD 鲁棒性，非常适合 1 V 低压应用。