Emerging spectrum trends require a higher integration of 5G New Radio Frequency Range 1 (FR1) and Frequency Range 2 (FR2) bands to enhance the availability of spectrum and spectrum-sharing opportunities. To enable the reception of both FR1 and FR2 bands in a seamless hardware entity, we propose combining homodyne and heterodyne architectures. This necessitates the incorporation of a down-converter module that transfers the incoming signals from FR2 bands down to FR1, ensuring compatibility with an FR1 direct-conversion receiver (DCR) for the final signal reception. The primary focus of this paper is the design and implementation of the required integrated down-converter. The module includes an integrated balun, a low-noise amplifier (LNA) with a bypass mode, a dual-mode mixer, and an intermediate frequency (IF) amplifier. The introduced bypass mode helps to further elevate the linearity performance compared to the nominal mode. The bypass mode is designed for joint communication and sensing operation to avoid the compression of the receiver. This work also incorporates a local oscillator (LO) signal distribution network with phase tuning elements using a mixed-signal approach. The circuit is implemented in a 22-nm CMOS process, and the active die area is 0.6 \(\text {mm}^\text {2}\). The measurements demonstrate that the implemented chip can efficiently perform the required frequency conversion over a wide frequency range of 18–28 GHz. Conversion gain of 4.5–7.5 dB, noise figure of 15–19.7 dB, 1 dB compression point (IP1dB) of − 16 to − 10 dBm, and input third-order intercept point (IIP3) of − 5 to 0 dBm are achieved. The measured IP1 dB and IIP3 for the bypass mode are +0.5 to +4.5 dBm and +8.5 to +10 dBm, respectively.

新兴频谱趋势需要更高程度地集成 5G 新无线电频率范围 1 (FR1) 和频率范围 2 (FR2) 频段，以提高频谱的可用性和频谱共享机会。为了能够在无缝硬件实体中接收 FR1 和 FR2 频段，我们建议结合零差和外差架构。这就需要结合一个下变频模块，将输入信号从 FR2 频段向下传输到 FR1，以确保与 FR1 直接变频接收器 (DCR) 的兼容性，以实现最终信号接收。本文的主要重点是所需集成下变频器的设计和实现。该模块包括集成巴伦、具有旁路模式的低噪声放大器 (LNA)、双模混频器和中频 (IF) 放大器。与标称模式相比，引入的旁路模式有助于进一步提升线性性能。旁路模式专为联合通信和传感操作而设计，以避免接收器的压缩。这项工作还采用混合信号方法将本地振荡器 (LO) 信号分配网络与相位调谐元件结合在一起。该电路采用 22 nm CMOS 工艺实现，有源芯片面积为 0.6  \(\text {mm}^\text {2}\)。测量结果表明，所实现的芯片可以在 18-28 GHz 的宽频率范围内高效地执行所需的频率转换。实现了 4.5–7.5 dB 的转换增益、15–19.7 dB 的噪声系数、− 16 至 − 10 dBm 的 1 dB 压缩点 (IP1dB) 以及 − 5 至 0 dBm 的输入三阶交调点 (IIP3)。旁路模式下测得的 IP1 dB 和 IIP3 分别为 +0.5 至 +4.5 dBm 和 +8.5 至 +10 dBm。