Abstract

Agile hardware design is gaining increasing momentum and bringing new chips in larger quantities to the market faster. However, it also takes new challenges for compiler developers to retarget existing compilers to these new chips in shorter time than ever before. Currently, retargeting a compiler backend, e.g., an LLVM backend to a new target, requires compiler developers to write manually a set of target description files (totalling 10 300+ lines of code (LOC) for RISC-V in LLVM), which is error-prone and time-consuming. In this paper, we introduce a new approach, Automatic Target Description File Generation (ATG), which accelerates the generation of a compiler backend for a new target by generating its target description files automatically. Given a new target, ATG proceeds in two stages. First, ATG synthesizes a small list of target-specific properties and a list of code-layout templates from the target description files of a set of existing targets with similar instruction set architectures (ISAs). Second, ATG requests compiler developers to fill in the information for each instruction in the new target in tabular form according to the list of target-specific properties synthesized and then generates its target description files automatically according to the list of code-layout templates synthesized. The first stage can often be reused by different new targets sharing similar ISAs. We evaluate ATG using nine RISC-V instruction sets drawn from a total of 1 029 instructions in LLVM 12.0. ATG enables compiler developers to generate compiler backends for these ISAs that emit the same assembly code as the existing compiler backends for RISC-V but with significantly less development effort (by specifying each instruction in terms of up to 61 target-specific properties only).

中文翻译：

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自动生成目标描述文件

摘要

敏捷硬件设计正在获得越来越大的动力，并更快地将大批量的新芯片推向市场。然而，对于编译器开发人员来说，如何在比以往更短的时间内将现有编译器重新定位到这些新芯片也面临着新的挑战。目前，将编译器后端（例如，LLVM 后端）重定向到新目标，需要编译器开发人员手动编写一组目标描述文件（LLVM 中的 RISC-V 总共 10 300 多行代码（LOC）），这是容易出错且耗时。在本文中，我们介绍了一种新方法，自动目标描述文件生成（ATG），它通过自动生成目标描述文件来加速新目标的编译器后端的生成。有了新目标，ATG 分两个阶段进行。首先，ATG 从一组具有相似指令集架构 (ISA) 的现有目标的目标描述文件中综合一小部分特定于目标的属性和一系列代码布局模板。其次，ATG要求编译器开发人员根据合成的目标特定属性列表以表格形式填写新目标中每条指令的信息，然后根据合成的代码布局模板列表自动生成其目标描述文件。第一阶段通常可以由共享相似 ISA 的不同新目标重用。我们使用从 LLVM 12.0 中总共 1029 条指令中提取的 9 个 RISC-V 指令集来评估 ATG。ATG 使编译器开发人员能够为这些 ISA 生成编译器后端，这些 ISA 发出与 RISC-V 现有编译器后端相同的汇编代码，但开发工作量显着减少（通过仅根据最多 61 个特定于目标的属性来指定每条指令）。