The emerging mobile robot industry has spurred a flurry of interest in solving the simultaneous localization and mapping (SLAM) problem. However, existing SLAM platforms have difficulty in meeting the real-time and low-power requirements imposed by mobile systems. Though specialized hardware is promising with regard to achieving high performance and lowering the power, designing an efficient accelerator for SLAM is severely hindered by a wide variety of SLAM algorithms. Based on our detailed analysis of representative SLAM algorithms, we observe that SLAM algorithms advance two challenges for designing efficient hardware accelerators: the large number of computational primitives and irregular control flows. To address these two challenges, we propose a hardware accelerator that features composable computation units classified as the matrix, vector, scalar, and control units. In addition, we design a hierarchical instruction set for coping with a broad range of SLAM algorithms with irregular control flows. Experimental results show that, compared against an Intel x86 processor, on average, our accelerator with the area of 7.41 mm² achieves 10.52x and 112.62x better performance and energy savings, respectively, across different datasets. Compared against a more energy-efficient ARM Cortex processor, our accelerator still achieves 33.03x and 62.64x better performance and energy savings, respectively.

新兴的移动机器人行业激发了人们对解决同步定位与地图构建（SLAM）问题的浓厚兴趣。然而，现有的SLAM平台难以满足移动系统的实时性和低功耗要求。尽管专用硬件在实现高性能和降低功耗方面很有希望，但设计高效的 SLAM 加速器却受到各种 SLAM 算法的严重阻碍。基于我们对代表性 SLAM 算法的详细分析，我们观察到 SLAM 算法为设计高效的硬件加速器提出了两个挑战：大量的计算原语和不规则的控制流。为了解决这两个挑战，我们提出了一种硬件加速器，其特点是可组合的计算单元分为矩阵、向量、标量和控制单元。此外，我们还设计了一个分层指令集，用于处理具有不规则控制流的各种 SLAM 算法。实验结果表明，与英特尔 x86 处理器相比，平均而言，我们的面积为 7.41 mm ²的加速器在不同数据集上分别实现了 10.52 倍和 112.62 倍的性能和节能效果。与更节能的 ARM Cortex 处理器相比，我们的加速器的性能和节能效果仍然分别提高了 33.03 倍和 62.64 倍。