Recent advancements in low power and low noise front-end amplifiers have made it possible to support high-speed data transmission within the deep roll-off regions of conventional wireline channels. Despite being primarily limited by inter-symbol-interference (ISI), these legacy channels also require power-consuming front-end amplifiers due to increased insertion-loss at high frequencies. Wireline-like broadband channels, such as proximity communication and human-body-communication (HBC), as well as multi-lane, densely-packed channels, are further constrained by their high loss and unique channel responses which cause the received signal to be noise-limited. To address these challenges, this paper proposes the use of a discrete-time integrating amplifier as a low power <1 pJ/b using 65nm CMOS up to 5-6 Gb/s) alternative to traditional continuous-time front-end amplifiers. Integrating amplifiers also reduce the effects of noise due to its inherent current integrating process. The paper provides a detailed mathematical analysis of gain of two conventional and three novel and improved integrating amplifiers, accurate input referred noise estimations, signal-to-noise ratio, and a comparison of the integrating amplifier’s performance with that of a low-noise amplifier. The analysis identifies the most optimum integrator architecture and provides comparison with simulated results. This paper also develops theoretical expressions and provides in-depth understanding of input referred noise, while supporting them by simulations using 65nm CMOS technology node. Finally, a comparative analysis between low-noise amplifier and discrete-time integrating amplifier is presented to demonstrate power and noise benefits for both legacy and wireline-like channels, while providing an easier design space as integrator provides two-dimensional controllability for gain.

中文翻译：

---

分析离散时间积分放大器作为宽带接收器中连续时间放大器的替代方案

低功耗和低噪声前端放大器的最新进展使得支持传统有线信道的深滚降区域内的高速数据传输成为可能。尽管主要受到符号间干扰 (ISI) 的限制，但由于高频插入损耗增加，这些传统通道还需要耗电的前端放大器。类似有线的宽带信道，例如近距离通信和人体通信（HBC），以及多通道、密集的信道，进一步受到其高损耗和独特的信道响应的限制，导致接收到的信号噪音有限。为了应对这些挑战，本文建议使用离散时间积分放大器作为传统连续时间前端放大器的替代品，该放大器采用 65nm CMOS，功耗 <1 pJ/b，速率高达 5-6 Gb/s。由于其固有的电流积分过程，积分放大器还可以减少噪声的影响。本文对两种传统积分放大器和三种新颖改进的积分放大器的增益、精确的输入参考噪声估计、信噪比以及积分放大器与低噪声放大器的性能进行了详细的数学分析。该分析确定了最佳的积分器架构，并提供与模拟结果的比较。本文还开发了理论表达式并提供了对输入参考噪声的深入理解，同时通过使用 65nm CMOS 技术节点的模拟来支持它们。最后，对低噪声放大器和离散时间积分放大器进行了比较分析，以证明传统通道和类似有线通道的功率和噪声优势，同时由于积分器提供了增益的二维可控性，因此提供了更简单的设计空间。