An atomic layer etching (ALE) process without purge has been developed for gate recess etching of AlGaN/GaN high electron mobility transistors (HEMTs). The process consists of repeating ALE cycles where Cl2/BCl3 plasma modifies the surface by chemisorption. The modified layer is removed by the subsequential Ar ion removal step. In this manner, AlGaN/GaN HEMTs with three different gate recess etching depths of (7.3 ± 0.5), (13.6 ± 0.5), and (21.0 ± 0.5) nm were fabricated. The determined etch per cycle (EPC) of ∼0.5 nm corresponding to one unit cell in the c-direction of GaN was constant for all recesses, illustrating the precision and controllability of the developed ALE process. The root-mean-square surface roughness was 0.3 nm for every etching depth, which corresponds to the roughness of the unetched reference. The electrical measurements show a linear dependence between threshold voltage (Vth) and etching depth. An enhancement mode (E-mode) HEMT was successfully achieved. A deeper gate recess than 20 nm leads to an increased channel resistance, lower saturation current, and higher gate leakage. Hence, a compromise between the desired Vth shift and device performance has to be reached. The achieved results of electrical and morphological measurements confirm the great potential of recess etching using the ALE technique with precisely controlled EPC for contact and channel engineering of AlGaN/GaN HEMTs.

中文翻译：

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通过免吹扫原子层蚀刻进行栅凹进 AlGaN/GaN 高电子迁移率晶体管器件的形貌和电学表征

开发出一种无需吹扫的原子层蚀刻 (ALE) 工艺，用于 AlGaN/GaN 高电子迁移率晶体管 (HEMT) 的栅极凹槽蚀刻。该过程包括重复 ALE 循环，其中 Cl2/BCl3 等离子体通过化学吸附对表面进行改性。通过随后的Ar离子去除步骤去除改性层。以这种方式，制备了具有（7.3±0.5）、（13.6±0.5）和（21.0±0.5）nm三种不同栅极凹槽蚀刻深度的AlGaN/GaN HEMT。所确定的每周期蚀刻 (EPC) 约为 0.5 nm，对应于 GaN c 方向上的一个晶胞，对于所有凹槽来说都是恒定的，这说明了所开发的 ALE 工艺的精度和可控性。每个蚀刻深度的均方根表面粗糙度为 0.3 nm，这对应于未蚀刻参考的粗糙度。电气测量显示阈值电压 (Vth) 和蚀刻深度之间存在线性相关性。成功实现了增强模式（E模式）HEMT。比 20 nm 更深的栅极凹槽会导致沟道电阻增加、饱和电流降低和栅极泄漏增加。因此，必须在所需的 Vth 偏移和器件性能之间达成折衷。所获得的电学和形态测量结果证实了使用 ALE 技术和精确控制的 EPC 进行凹槽蚀刻在 AlGaN/GaN HEMT 的接触和沟道工程中的巨大潜力。