Implementing large capacitors in integrated circuits demands an occupation of a relatively significant large silicon area on-chip, which strictly limits the capability of the physical implementation of low-frequency integrated circuits that mostly require high capacitance values to provide large time-constants. Capacitance multipliers have been proposed to overcome this issue to realize high-value active capacitances in a small chip area. This paper proposes a new current-mode ultra-low power capacitance multiplier based on the floating capacitance Super Flipped Current Follower (SFCF) circuit which employs two AB class cascaded stages. The main novel idea behind the proposed circuit is combining the cross-coupling Quasi-Floating Gate (QFG) with the class-AB techniques and employing the Super Flipped Current Follower (SFCF) circuit, to enhance the adjustment efficiency ratio (M) factor, while also achieving a high scaling factor “K”. As a result, the proposed circuit achieves higher K value at the lower power and chip size area costs, while providing better adjustment efficiency ratio (M), which realizes a better “capacitance adjustability-power” trade-off. The proposed circuit provides other advantages such as: wide electronic tunability of scaling factor K, large Parallel Load Resistance (PLR) value, small value of Equivalent Series Resistance (ESR), relatively small chip size area, and a high ratio of adjustment efficiency (M). The total power consumption of the proposed circuit is obtained as 101 nW, using a base capacitance (C) of 1 pF, which leads to the realization of a maximum achievable equivalent capacitance (C) of 1604 pF. In addition, the performance of the proposed tunable capacitance multiplier is examined in the realization of a wide-tunable low-pass filter structure. Furthermore, the performance robustness of the proposed circuit is investigated by the Monte-Carlo and PVT analyses in different technology corners, which justify the good performance of the proposed circuit that makes it a proper candidate to be used in ultra-low power biomedical signal processing.

中文翻译：

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一种用于生物医学应用的亚阈值区新型超低功耗宽可调电容乘法器电路

在集成电路中实现大电容器需要占用相对较大的片上硅面积，这严格限制了低频集成电路的物理实现的能力，低频集成电路大多需要高电容值来提供大时间常数。已经提出电容倍增器来克服这个问题，以在小芯片面积中实现高值有源电容。本文提出了一种基于浮动电容超级翻转电流跟随器（SFCF）电路的新型电流模式超低功耗电容倍增器，该电路采用两个AB级级联级。该电路背后的主要新颖思想是将交叉耦合准浮栅（QFG）与AB类技术相结合，并采用超级翻转电流跟随器（SFCF）电路，以提高调节效率比（M）系数，同时还实现了高比例因子“K”。因此，所提出的电路以较低的功耗和芯片尺寸面积成本实现了较高的K值，同时提供了更好的调节效率比（M），从而实现了更好的“电容可调节性-功率”权衡。所提出的电路还具有其他优点，例如：比例因子 K 的电子可调性宽、并联负载电阻（PLR）值大、等效串联电阻（ESR）值小、芯片尺寸面积相对较小以及调节效率比（米）。使用 1 pF 的基础电容 (C) 时，所提出电路的总功耗为 101 nW，从而实现了 1604 pF 的最大可实现等效电容 (C)。此外，在实现宽可调低通滤波器结构时检查了所提出的可调电容乘法器的性能。此外，通过蒙特卡罗和 PVT 分析在不同技术领域研究了所提出电路的性能鲁棒性，这证明了所提出电路的良好性能，使其成为超低功耗生物医学信号处理的合适候选者。 。