To perform classification for a particular application, a Decision Tree (DT) model first needs to be trained using that application data. Due to high complexity, DT training implemented on software platforms is time-consuming. So, hardware platforms like Field Programmable Gate Array (FPGA) and Application Specific Integrated Circuits (ASICs) can be used to accelerate the process. Also, DT training hardware can be used for a different application simply by altering the training data. The hardware cost can be reduced by optimizing and reducing the training complexity. Thus, this paper proposes a pipelined architecture for low complexity Hybrid Decision Tree (HDT) algorithm. The maximum operating frequency of the proposed hardware is found to be 200 MHz on FPGA. Simulation results show that FPGA-based implementation is at least faster than the C-based realization. ASIC implementation of the design occupies a total area of MHz as synthesized on UMC technology node and hence suitable for portable devices.

中文翻译：

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适用于便携式设备的流水线训练加速器

要对特定应用程序进行分类，首先需要使用该应用程序数据来训练决策树 (DT) 模型。由于复杂性高，在软件平台上实施的DT训练非常耗时。因此，可以使用现场可编程门阵列 (FPGA) 和专用集成电路 (ASIC) 等硬件平台来加速这一过程。此外，只需更改训练数据，DT 训练硬件即可用于不同的应用。通过优化和降低训练复杂度可以降低硬件成本。因此，本文提出了一种低复杂度混合决策树（HDT）算法的流水线架构。所提出的硬件在 FPGA 上的最大工作频率为 200 MHz。仿真结果表明基于FPGA的实现至少比基于C的实现要快。该设计的 ASIC 实现占用了在 UMC 技术节点上综合的 MHz 总面积，因此适用于便携式设备。