This work presents an analytical model for the drain and gate currents of silicon nanowire and nanosheet MOS transistors valid in all operating regions in the temperature range from 300 to 500 K. Analytical models for the tunneling components as well as for the reversely biased drain‐to‐channel PN junction are presented. Also, the models accounting for the necessary modifications in the silicon physical quantities for high‐temperature operation, such as the maximum carrier mobility, the bandgap, and the intrinsic carrier concentration, are presented. The proposed model uses a single set of parameters, extracted at room temperature, to describe the high‐temperature operation of silicon nanowire MOSFETs. The model is validated with comparisons between modeled and experimental results for devices with different fin widths and operating temperatures, with good agreement.

中文翻译：

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硅纳米线和纳米片 MOS 晶体管漏极和栅极电流的分析模型在 300 到 500 K 之间有效

这项工作提出了硅纳米线和纳米片 MOS 晶体管漏极和栅极电流的分析模型，该模型在 300 至 500 K 温度范围内的所有工作区域均有效。隧道元件以及反向偏置漏极到晶体管的分析模型‐通道 PN 结出现。此外，还提出了考虑高温操作时硅物理量必要修改的模型，例如最大载流子迁移率、带隙和本征载流子浓度。所提出的模型使用在室温下提取的一组参数来描述硅纳米线 MOSFET 的高温运行。通过比较具有不同翅片宽度和工作温度的器件的模型结果和实验结果，对该模型进行了验证，具有良好的一致性。