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A 16-Gb/s Baud-Rate CDR Circuit With One-Tap Speculative DFE and Wide Frequency Capture Range
IEEE Transactions on Very Large Scale Integration (VLSI) Systems ( IF 2.8 ) Pub Date : 2024-01-25 , DOI: 10.1109/tvlsi.2024.3353197
Po-Yuan Chou, Wei-Ming Chen, Shen-Iuan Liu

A 16-Gb/s baud-rate clock and data recovery (CDR) circuit with a one-tap decision-feedback equalizer (DFE) and a wide frequency capture range (FCR) is presented. The proposed asymmetrical pattern-based phase detectors are used to achieve a wide FCR. This quarter-rate CDR circuit is fabricated in 40-nm CMOS technology and the active area is 0.1094 mm2. For a 16 Gb/s PRBS of 27–1, the power of the CDR circuit is 38.4 mW and its calculated energy efficiency is 2.4 pJ/b. The measured FCR is 40.6%.

中文翻译:

具有一键推测 DFE 和宽频率捕获范围的 16 Gb/s 波特率 CDR 电路

提出了一种具有单抽头判决反馈均衡器 (DFE) 和宽频率捕获范围 (FCR) 的 16 Gb/s 波特率时钟和数据恢复 (CDR) 电路。所提出的基于非对称图案的相位检测器用于实现宽 FCR。该四分之一速率 CDR 电路采用 40 nm CMOS 技术制造,有效面积为 0.1094 mm2。对于 27-1 的 16 Gb/s PRBS,CDR 电路的功率为 38.4 mW,计算出的能效为 2.4 pJ/b。测得的FCR为40.6%。
更新日期:2024-01-25
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