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A light-weight neuromorphic controlling clock gating based multi-core cryptography platform
Microprocessors and Microsystems ( IF 2.6 ) Pub Date : 2024-02-26 , DOI: 10.1016/j.micpro.2024.105040
Pham-Khoi Dong , Khanh N. Dang , Duy-Anh Nguyen , Xuan-Tu Tran

While speeding up cryptography tasks can be accomplished by using a multi-core architecture to parallelize computation, one of the major challenges is optimizing power consumption. In principle, depending on the computation workload, individual cores can be turned off to save power during operation. However, too few active cores may lead to computational bottlenecks. In this work, we propose a novel platform named Spike-MCryptCores: a low-power multi-core AES platform with a neuromorphic controller. The proposed Spike-MCryptCores platform is composed of multiple AES cores, each core is equipped with a clock-gating scheme for reducing its power consumption while being idle. To optimize the power consumption of the whole platform, we use a neuromorphic controller. Therefore, a comprehensive framework to generate a data set, train the neural network, and produce hardware configuration for the Spiking Neural Network (SNN), a brain-inspired computing paradigm, is also presented in this paper. Moreover, Spike-MCryptCores integrates the hardware SNN inside its architecture to support low-cost and low-latency adaptations. The results show that implemented SNN controller occupies only 2.3 % of the overall area cost while providing the ability to reduce power consumption significantly. The lightweight SNN controller model is trained and tested with up to 95 % accuracy. The maximum difference between the predicted number of cores and the ideal one from the label is one unit only. Under 24 test scenarios, a SNN controller with clock-gating helps Spike-MCryptCores reducing the power consumption by 48.6 % on the average; by 67 % for the best-case scenario, and by 39 % for the worst-case scenario.

中文翻译:

基于轻量级神经形态控制时钟门控的多核密码平台

虽然可以通过使用多核架构并行计算来加速加密任务,但主要挑战之一是优化功耗。原则上,根据计算工作量,可以在运行期间关闭各个内核以节省电量。然而,活动核心太少可能会导致计算瓶颈。在这项工作中,我们提出了一个名为 Spike-MCryptCores 的新颖平台:带有神经形态控制器的低功耗多核 AES 平台。所提出的 Spike-MCryptCores 平台由多个 AES 内核组成,每个内核都配备了时钟门控方案,以降低空闲时的功耗。为了优化整个平台的功耗,我们使用了神经形态控制器。因此,本文还提出了一个综合框架,用于生成数据集、训练神经网络并为尖峰神经网络(SNN)(一种类脑计算范式)生成硬件配置。此外,Spike-MCryptCores在其架构中集成了硬件SNN,以支持低成本和低延迟的适配。结果表明,所实现的 SNN 控制器仅占用总体面积成本的 2.3%,同时能够显着降低功耗。轻量级 SNN 控制器模型经过训练和测试,准确率高达 95%。预测核心数与标签上的理想核心数之间的最大差异仅为 1 个单位。在24种测试场景下,带有时钟门控的SNN控制器帮助Spike-MCryptCores平均降低了48.6%的功耗;最好情况下减少 67%,最坏情况下减少 39%。
更新日期:2024-02-26
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