Abstract

In this paper, methods for increasing the efficiency of VLSI development based on the method of architecture-independent design are proposed. The route of high-level VLSI synthesis is considered. The principle of constructing a VLSI hardware model based on the functional-flow programming paradigm is stated. The results of the development of methods and algorithms for the transformation of functional-parallel programs into programs in HDL languages that support the design process of digital chips are presented. The principles of assessment are considered and the classes of resources required for the analysis of design solutions are identified. Reduction coefficients and methods of their calculation for each resource class are introduced. An algorithm for calculating the reduction coefficients and estimating the required resources is proposed. An algorithm for converting parallelism is proposed, taking into account the specified constraints of the target platform. A mechanism for the exchange of metrics with an architecture-dependent level is developed. Examples of the reduction of parallelism for the FPGA platform and practical implementation of FFT algorithms in the Virtex® UltraScale FPGA basis are given. The developed methods and algorithms make it possible to use the method of architecture-independent synthesis for transferring VLSI projects to various architectures by changing the parallelism of the circuit and equivalent transformations of parallel programs. The proposed approach provides many options for hardware solutions for implementation on various target platforms.

中文翻译：

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高级VLSI综合过程中改变并行度的方法

摘要

本文提出了基于架构无关设计方法来提高VLSI开发效率的方法。考虑了高级VLSI合成的路线。阐述了基于功能流编程范式构建VLSI硬件模型的原理。介绍了将功能并行程序转换为支持数字芯片设计过程的 HDL 语言程序的方法和算法的开发结果。考虑评估原则并确定分析设计解决方案所需的资源类别。介绍了各资源类别的折减系数及其计算方法。提出了一种计算缩减系数并估计所需资源的算法。考虑到目标平台的指定约束，提出了一种转换并行度的算法。开发了一种与体系结构相关的级别交换度量的机制。给出了减少 FPGA 平台并行性以及在 Virtex® UltraScale FPGA 基础上实际实现 FFT 算法的示例。所开发的方法和算法使得使用与体系结构无关的综合方法通过改变电路的并行性和并行程序的等效变换将VLSI项目转移到各种体系结构成为可能。所提出的方法为在各种目标平台上实现的硬件解决方案提供了许多选项。