This paper describes a ultra-wideband (UWB) three-stage cascaded high gain amplifier with low group delay variation for phased-array radar system. The shunt inductor at the input not only provides an electrostatic discharge (ESD) path to ground, but also introduces a new notch for , thus extending the matching bandwidth. Staggered tuning of load impedance peaks at each stage facilitates a balance between flat gain and low group delay variation. The output stage further enhances the overall gain while reinforcing bandwidth and stability through resistive feedback, and employs an adaptive bias circuit for linearity improvement. Implemented in SMIC 40-nm CMOS technology, the proposed amplifier achieves good input impedance matching, flat gain and low group delay variation of ±73.5 ps over 4.7–16 GHz. The whole power consumption is 198.3 mW and the output 1 dB compression point (OP) is greater than 9 dBm. After careful design, the chip size is 0.64 mm.

中文翻译：

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用于相控阵雷达系统的超宽带高增益低群延迟变化放大器

本文介绍了一种用于相控阵雷达系统的低群时延变化的超宽带 (UWB) 三级级联高增益放大器。输入端的并联电感不仅提供接地静电放电 (ESD) 路径，还引入了新的陷波器，从而扩展了匹配带宽。每级负载阻抗峰值的交错调谐有利于平坦增益和低群延迟变化之间的平衡。输出级进一步增强了整体增益，同时通过电阻反馈增强了带宽和稳定性，并采用自适应偏置电路来改善线性度。该放大器采用 SMIC 40 nm CMOS 技术实现，可实现良好的输入阻抗匹配、平坦增益以及在 4.7-16 GHz 范围内 ±73.5 ps 的低群延迟变化。整体功耗为198.3 mW，输出1 dB压缩点（OP）大于9 dBm。经过精心设计，芯片尺寸为0.64毫米。