This research work focuses on implementation of the FinFET-based complementary metal-oxide-semiconductor (CMOS) Full Adder circuits for different transistor configurations using ASAP7 FinFET model. First, this work examines FinFET-based AND-OR-invert (AOI) gates using different topologies, and second, a FinFET-based CMOS Full Adder circuit at the 7$$nm technology node is analyzed with respect to its process, voltage and temperature (PVT) variability effect measured in terms of the normalized standard deviation of different performance metrics. The comparison is made between conventional (CFFA1) and proposed (FFA2, FFA3, FFA4, FFA5, FFA6, FFA7 and FFA8) FinFET-based CMOS full adder circuits. The aim is to determine the optimal design configuration of the FinFET full adder circuit with the minimum impact of PVT variability. On examining the power delay product (PDP) variability, it is found that variations in FFA2, FFA3, FFA4, FFA5, FFA6, FFA7 and FFA8 are significantly lower than CFFA1 by 6.30%, 4.68%, 10.30%, 65.48%, 68.05%, 65.61% and 17.20%, respectively. Among all the proposed configurations, normalized standard deviation $\sigma /\mu (\%)$ for the PDP metric is lowest in FFA6, followed by FFA7, FFA5, FFA8, FFA4, FFA2 and FFA3. The normalized standard deviation $\sigma /\mu (\%)$ for power dissipation, however, is lowest in FFA8. In addition, a layout comparison analysis of conventional and proposed full adder circuits reveals that FFA7 has the least area, followed by FFA8, FFA6, FFA5, FFA3, FFA4, FFA2 and CFFA1. The area of FFA2, FFA3, FFA4, FFA5 and FFA6 has decreased by 3.29%, 3.51%, 3.50%, 5.14% and 5.52%, while FFA7 and FFA8 have experienced a decrease in area by 13.87% and 14.36%, respectively, as compared to conventional CFFA1. The proposed layout of FinFET-based CMOS Full Adders can be directly transferred into the foundry’s production line for manufacturing purposes. The overall investigation led us to conclude that FFA8 is the most efficient of all due to the lowest power variation, lower delay variation and lower PDP variation, moreover it has a reduced layout area among all the discussed designs. However, there is a tradeoff in terms of penalty in nominal power, propagation delay and PDP in the proposed topologies.

这项研究工作的重点是使用 ASAP7 FinFET 模型针对不同晶体管配置实现基于 FinFET 的互补金属氧化物半导体 (CMOS) 全加器电路。首先，这项工作研究了使用不同拓扑的基于 FinFET 的与或反转 (AOI) 门，其次，研究了基于 FinFET 的 CMOS 全加器电路（7$$纳米技术节点的工艺、电压和温度（PVT）变异性影响是根据不同性能指标的标准化标准差来测量的。对传统 (CFFA1) 和建议的 (FFA2、FFA3、FFA4、FFA5、FFA6、FFA7 和 FFA8) 基于 FinFET 的 CMOS 全加器电路进行了比较。目的是确定 FinFET 全加器电路的最佳设计配置，同时将 PVT 变化的影响降至最低。在检查功率延迟乘积（PDP）变异性时，发现FFA2、FFA3、FFA4、FFA5、FFA6、FFA7和FFA8的变异性显着低于CFFA1，分别为6.30%、4.68%、10.30%、65.48%、68.05%分别为 65.61% 和 17.20%。在所有建议的配置中，归一化标准差$\sigma /\mu （\%）$PDP 指标在 FFA6 中最低，其次是 FFA7、FFA5、FFA8、FFA4、FFA2 和 FFA3。归一化标准差$\sigma /\mu （\%）$然而，FFA8 中的功耗最低。此外，对传统全加器电路和提出的全加器电路的布局比较分析表明，FFA7的面积最小，其次是FFA8、FFA6、FFA5、FFA3、FFA4、FFA2和CFFA1。FFA2、FFA3、FFA4、FFA5和FFA6的面积分别减少了3.29%、3.51%、3.50%、5.14%和5.52%，而FFA7和FFA8的面积分别减少了13.87%和14.36%。与传统的 CFFA1 相比。基于 FinFET 的 CMOS 全加器的拟议布局可以直接转移到代工厂的生产线中用于制造目的。整体调查使我们得出结论，FFA8 是所有设计中效率最高的，因为它具有最低的功率变化、较低的延迟变化和较低的 PDP 变化，而且它在所有讨论的设计中具有较小的布局面积。然而，在所提出的拓扑中，在标称功率、传播延迟和 PDP 的损失方面存在权衡。