Near-memory computing (NMC) and in- memory computing (IMC) paradigms show great importance in non-von Neumann architecture. Spin-transfer torque magnetic random access memory (STT-MRAM) is considered as a promising candidate to realize both NMC and IMC for resource-constrained applications. In this work, two MRAM-centric computing frameworks are proposed: triple-skipping NMC (TS-NMC) and analog-multi-bit-sparsity IMC (AMS-IMC). The TS-NMC exploits the sparsity of activations and weights to implement a write-read-calculation triple skipping computing scheme by utilizing a sparse flag generator. The AMS-IMC with reconfigured computing bit-cell and flag generator accommodate bit-level activation sparsity in the computing. STT-MRAM array and its peripheral circuits are implemented with an industrial 28-nm CMOS design-kit and an MTJ compact model. The triple-skipping scheme can reduce memory access energy consumption by 51.5× when processing zero vectors, compared to processing non-zero vectors. The energy efficiency of AMS-IMC is improved by 5.9× and 1.5× (with 75% input sparsity) as compared to the conventional NMC framework and existing analog IMC framework. Verification results show that TS-NMC and AMS-IMC achieved 98.6% and 97.5% inference accuracy in MNIST classification, with energy consumption of 14.2 nJ/pattern and 12.7 nJ/pattern, respectively.

中文翻译：

---

用于高效神经网络推理的面向稀疏性的以 MRAM 为中心的计算

近内存计算（NMC）和内存计算（IMC）范式在非冯诺依曼架构中表现出非常重要的作用。自旋转移矩磁性随机存取存储器（STT-MRAM）被认为是在资源受限的应用中实现 NMC 和 IMC 的有前途的候选者。在这项工作中，提出了两种以 MRAM 为中心的计算框架：三重跳跃 NMC (TS-NMC) 和模拟多位稀疏 IMC (AMS-IMC)。TS-NMC 利用激活和权重的稀疏性，通过稀疏标志生成器来实现写-读-计算三重跳跃计算方案。具有重新配置的计算位单元和标志生成器的 AMS-IMC 可适应计算中的位级激活稀疏性。STT-MRAM 阵列及其外围电路采用工业 28 nm CMOS 设计套件和 MTJ 紧凑型模型来实现。与处理非零向量相比，三重跳跃方案在处理零向量时可以减少 51.5 倍的内存访问能耗。与传统 NMC 框架和现有模拟 IMC 框架相比，AMS-IMC 的能效提高了 5.9 倍和 1.5 倍（输入稀疏度为 75%）。验证结果显示，TS-NMC和AMS-IMC在MNIST分类中的推理准确率达到98.6%和97.5%，能耗分别为14.2 nJ/pattern和12.7 nJ/pattern。