Incorporating PowerVia in SRAM arrays has added challenges as it requires large design changes to the circuit, while — in comparison to logical applications — congestion at the frontside is less of a limiting factor and voltage droop is less important because typically only a fraction of memory devices need to activate at any one time. Daeyeon Kim and colleagues at Intel now report six-transistor SRAM arrays with PowerVia using a 7-nm process.

The researchers used an ‘around-the-array’ scheme for the PowerVia technology. The vias are located at transition regions between the SRAM bitcells and logic circuits, and then routed to individual bitcells using connections at the frontside. The team created a 108 Mb high-current SRAM and a 124 Mb high-density SRAM design, with the former showing a 2% area reduction compared with similar arrays with a conventional power scheme.

将 PowerVia 纳入 SRAM 阵列增加了挑战，因为它需要对电路进行大量设计更改，而与逻辑应用相比，前端的拥塞并不是一个限制因素，而且电压下降也不那么重要，因为通常只有一小部分存储设备需要随时激活。英特尔的 Daeyeon Kim 和同事现在报告了采用 7 纳米工艺的 PowerVia 六晶体管 SRAM 阵列。

研究人员对 PowerVia 技术使用了“环绕阵列”方案。通孔位于 SRAM 位单元和逻辑电路之间的过渡区域，然后使用前端的连接布线到各个位单元。该团队创建了 108 Mb 高电流 SRAM 和 124 Mb 高密度 SRAM 设计，与采用传统电源方案的类似阵列相比，前者的面积减少了 2%。