Remora Optimized Dynamic Neural Network to Design Low-Power CNTFET Logic Gate Realization with Multiple-Valued Circuits,Electric Power Components and Systems

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Remora Optimized Dynamic Neural Network to Design Low-Power CNTFET Logic Gate Realization with Multiple-Valued Circuits
Electric Power Components and Systems ( IF 1.5 ) Pub Date : 2024-03-18 , DOI: 10.1080/15325008.2024.2326854
Sriram Sandhya Rani ₁ , Hameed Pasha Mohammad ₁ , Sheik Masthan ₁

Affiliation

The emerging trend of new digital technology leads to the requirement of small, faster, and low-power consumed processors. The advanced 5 G technology forces the usage of enhanced battery life, max...

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