In this paper, the analysis and design process of the voltage‐source parallel resonant class E frequency multiplier with a 50% duty ratio is proposed. The proposed circuit adopts two series resonant filters for reducing the interference of harmonics to the output waveform and achieves zero‐voltage switching (ZVS) and zero‐voltage derivation switching (ZVDS) conditions. The design equations for the proposed circuit are given in detail. The new type class E frequency multiplier can operate at lower transistor voltage stress, higher operating frequency, and larger output power. Meanwhile, the volume and weight of the measured circuit are greatly decreased compared to the conventional class E frequency multiplier. To demonstrate the analysis process, the circuit operating at 1 MHz is fabricated and measured. Compared to the traditional class E frequency multiplier, the transistor peak voltage is reduced by 47.9%, the diameter of the resonant inductor core is decreased by 56.2%, and the measured efficiency can reach 95.1%. The theoretical and simulated results are all agreed with the experimental results.

中文翻译：

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电压源并联谐振E类倍频器的分析与设计

本文提出了占空比为50%的电压源并联谐振E类倍频器的分析和设计过程。该电路采用两个串联谐振滤波器来减少谐波对输出波形的干扰，并实现零电压开关（ZVS）和零电压微分开关（ZVDS）条件。详细给出了所提出电路的设计方程。新型E类倍频器可以在更低的晶体管电压应力下工作、更高的工作频率和更大的输出功率。同时，与传统的E类倍频器相比，被测电路的体积和重量也大大减小。为了演示分析过程，我们制作并测量了工作频率为 1 MHz 的电路。与传统E类倍频器相比，晶体管峰值电压降低了47.9%，谐振电感磁芯直径减小了56.2%，实测效率可达95.1%。理论和模拟结果均与实验结果吻合。