Abstract

Memristive devices have become promising candidates to complement the CMOS technology, due to their CMOS manufacturing process compatibility, zero standby power consumption, high scalability, as well as their capability to implement high-density memories and new computing paradigms. Despite these advantages, memristive devices are susceptible to manufacturing defects that may cause faulty behaviors not observed in CMOS technology, significantly increasing the challenge of testing these novel devices after manufacturing. This work proposes an optimized Design-for-Testability (DfT) strategy based on the introduction of a DfT circuitry that measures the current consumption of Resistive Random Access Memory (ReRAM) cells to detect not only traditional but also unique faults. The new DfT circuitry was validated using a case study composed of a 3x3 word-based ReRAM with peripheral circuitry implemented based on a 130 nm Predictive Technology Model (PTM) library. The obtained results demonstrate the fault detection capability of the proposed strategy with respect to traditional and unique faults. In addition, this paper evaluates the impact related to the DfT circuitry’s introduced overheads as well as the impact of process variation on the resolution of the proposed DfT circuitry.

中文翻译：

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保证 ReRAM 制造后质量的 DfT 策略

摘要

由于忆阻器件具有 CMOS 制造工艺兼容性、零待机功耗、高可扩展性以及实现高密度存储器和新计算范例的能力，忆阻器件已成为补充 CMOS 技术的有希望的候选者。尽管有这些优点，忆阻器件仍然容易受到制造缺陷的影响，这些缺陷可能会导致 CMOS 技术中未观察到的错误行为，从而显着增加了制造后测试这些新颖器件的挑战。这项工作提出了一种优化的可测试性设计 (DfT) 策略，该策略基于引入 DfT 电路，该电路测量电阻式随机存取存储器 (ReRAM) 单元的电流消耗，不仅可以检测传统故障，还可以检测独特的故障。新的 DfT 电路通过案例研究进行了验证，该案例研究由基于 3x3 字的 ReRAM 和基于 130 nm 预测技术模型 (PTM) 库实现的外围电路组成。获得的结果证明了所提出的策略对于传统和独特故障的故障检测能力。此外，本文还评估了与 DfT 电路引入的开销相关的影响，以及工艺变化对所提出的 DfT 电路分辨率的影响。