This article presents the experimental characterization and modeling of CMOS resistors in a temperature range extending from room temperature (300 K) down to the deep cryogenic regime at 4 K. A set of poly-silicon resistors with different bulk structures and sizing have been fabricated in a 65 nm CMOS process and their I–V curves have been obtained experimentally in the 4 to 300 K range with a temperature step of only 0.5 K to obtain a large set of resistance values equally distributed along the temperature range. The plot of the resistance values against temperature has allowed us to obtain the temperature coefficient $\alpha (T)$ of the different resistors in the whole temperature range down to 4 K. Interestingly, for all the measured resistors the $\alpha (T)$ –T curves show a change in tendency for temperatures spanning from 66 to 98 K, this is, in the vicinity of the condensation temperature of nitrogen (77 K), where most of the thermal contraction of materials occurs.

中文翻译：

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低温状态下 65 nm CMOS 集成电阻器的表征

本文介绍了 CMOS 电阻器在从室温 (300 K) 到 4 K 深冷状态的温度范围内的实验表征和建模。一组具有不同体结构和尺寸的多晶硅电阻器已在65 nm CMOS 工艺及其 I-V 曲线已在 4 至 300 K 范围内通过实验获得，温度步长仅为 0.5 K，以获得沿温度范围均匀分布的大量电阻值。电阻值与温度的关系图使我们能够获得温度系数 $\阿尔法(T)$不同电阻器在低至 4 K 的整个温度范围内的变化。有趣的是，对于所有测量的电阻器 $\阿尔法(T)$ –T 曲线显示温度范围从 66 K 到 98 K 的变化趋势，即在氮气凝结温度 (77 K) 附近，大多数材料的热收缩发生在此处。