Computing in-memory (CiM) is an alternative to von-Neumann architectures for energy efficient AI edge computing architectures with CMOS scaling. Approximate computing in-memory (ACiM) techniques have also been recently proposed to further increase the energy efficiency of such architectures. In the first part of the work, a negative capacitance FET (NCFET) based 6T-SRAM CiM accurate full adder has been proposed, designed and performance benchmarked with equivalent baseline 40 nm CMOS design. Due to the steep slope characteristics of NCFET, at an increased ferroelectric layer thickness, T _fe of 3 nm, the energy consumption of the proposed accurate NCFET based CiM design is ∼82.48% lower in comparison to the conventional/Non CiM full adder design and ∼85.27% lower energy consumption in comparison to the equivalent baseline CMOS CiM accurate full adder design at V _DD = 0.5 V. This work further proposes a reconfigurable computing in-memory NCFET 6T-SRAM full adder design (the design which can operate both in accurate and approximate modes of operation). NCFET 6T-SRAM reconfigurable full adder design in accurate mode has ∼4.19x lower energy consumption and ∼4.47x lower energy consumption in approximation mode when compared to the baseline 40 nm CMOS design at V _DD = 0.5 V, making NCFET based approximate CiM adder designs preferable for energy efficient AI edge CiM based computing architectures for DNN processing.

中文翻译：

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使用负电容 FET 6T-SRAM 计算内存中可重构（精确/近似）加法器设计，用于节能 AI 边缘设备

内存计算 (CiM) 是冯诺依曼架构的替代方案，适用于具有 CMOS 缩放功能的节能 AI 边缘计算架构。最近还提出了内存中近似计算（ACiM）技术来进一步提高此类架构的能源效率。在工作的第一部分中，提出、设计了基于负电容 FET (NCFET) 的 6T-SRAM CiM 精确全加器，并使用等效基线 40 nm CMOS 设计进行了性能基准测试。由于 NCFET 的陡坡特性，在增加铁电层厚度时，时间 _fe为 3 nm，与传统/非 CiM 全加器设计相比，所提出的基于 NCFET 的精确 CiM 设计的能耗降低了约 82.48%，与等效基线 CMOS CiM 精确全加器相比能耗降低了约 85.27%设计于V _DD = 0.5 V。这项工作进一步提出了一种可重构计算内存中 NCFET 6T-SRAM 全加器设计（该设计可以在精确和近似操作模式下运行）。与基准 40 nm CMOS 设计相比，精确模式下的 NCFET 6T-SRAM 可重配置全加器设计的能耗降低了约 4.19 倍，近似模式下的能耗降低了约 4.47 倍。V _DD = 0.5 V，使得基于 NCFET 的近似 CiM 加法器设计更适合用于 DNN 处理的节能 AI 边缘基于 CiM 的计算架构。