In the domain of process virtual machine (PVM) binary translation, the difference in address space layout between the guest program and the translated program requires the recalculation of jump instruction targets, resulting in suboptimal execution efficiency. This paper presents a novel method called SPC-Indexed Indirect Branch Hardware Cache Redirecting (SPCIC) technique. SPCIC utilizes specialized branch instruction to represent indirect branches from guest programs while frequently-used target addresses are cached in a customized hardware mapping table. When translating an indirect branch, SPCIC queries the jump target cache first to achieve a fast redirection unless the destination address is not cached. Besides, SPCIC merely falls back to the software-based remapping approach when the query fails, improving the translation efficiency to the greatest extent. SPCIC is implemented on the QEMU platform to accelerate the translation of ARM payloads into RISC-V. Experiments are carried on SPEC2006 to demonstrate the effectiveness of SPCIC for reducing the runtime overhead of indirect branch translation. The experimental results indicate up to 11% average improvement and 35% maximum improvement are obtained on the selected benchmark.

在进程虚拟机（PVM）二进制翻译领域，客户程序和翻译后的程序之间地址空间布局的差异需要重新计算跳转指令目标，导致执行效率不佳。本文提出了一种称为 SPC 索引间接分支硬件缓存重定向 (SPCIC) 技术的新颖方法。 SPCIC 利用专门的分支指令来表示来自客户程序的间接分支，而常用的目标地址则缓存在定制的硬件映射表中。在转换间接分支时，SPCIC 首先查询跳转目标缓存以实现快速重定向，除非目标地址没有缓存。此外，SPCIC在查询失败时仅回退到基于软件的重映射方法，最大程度地提高了翻译效率。 SPCIC 在 QEMU 平台上实现，以加速 ARM 有效负载到 RISC-V 的转换。在SPEC2006上进行了实验，证明了SPCIC对于减少间接分支翻译运行时开销的有效性。实验结果表明，在所选基准上获得了高达 11% 的平均改进和 35% 的最大改进。