In the emerging field of in-memory computing (IMC), this study proposes a dual-port static random access memory (SRAM) IMC architecture with the distinct capability of realizing XOR encryption (XORE), thus serving as a potential solution for the Von Neumann bottleneck. Beyond providing traditional SRAM read and write operations, the proposed architecture carries out additional tasks such as multi-bit multiply and accumulate (MAC) and XOR accumulation (XORA). The architecture was simulated using a 28-nm Complementary Metal Oxide Semiconductor Process, demonstrating a minor standard deviation of 9.41 mV in bit line voltage at the SS process corner, as evidenced by Monte Carlo simulation. Energy expenditure for the MAC, XORA, and XORE, was found to be 1.65, 1.46, and 9.02 fJ/ops respectively at the TT process corner. Furthermore, the presented architecture showed considerable energy efficiency, with MAC, XORA, and XORE operations achieving energy efficiency values of 604.9, 682.7, and 110.8 TOPS/W respectively, at a supply voltage of 0.9 V at the TT process corner.

中文翻译：

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基于双端口SRAM的可配置内存计算架构

在新兴的内存计算（IMC）领域，本研究提出了一种双端口静态随机存取存储器（SRAM）IMC架构，具有实现异或加密（XORE）的独特能力，从而成为Von的潜在解决方案诺伊曼瓶颈。除了提供传统的 SRAM 读写操作之外，所提出的架构还执行额外的任务，例如多位乘法累加 (MAC) 和异或累加 (XORA)。该架构使用 28 nm 互补金属氧化物半导体工艺进行仿真，结果表明 SS 工艺拐角处的位线电压存在 9.41 mV 的小标准偏差，蒙特卡洛仿真证明了这一点。在 TT 工艺角落，MAC、XORA 和 XORE 的能量消耗分别为 1.65、1.46 和 9.02 fJ/ops。此外，所提出的架构显示出相当大的能效，在 TT 工艺角落的电源电压为 0.9 V 时，MAC、XORA 和 XORE 操作分别实现了 604.9、682.7 和 110.8 TOPS/W 的能效值。