This work presents an approach to extract and analytically model the components of the parasitic capacitance in the Nanosheet FETs. The model comprehensively accounts for parallel, fringing, and junction capacitance between the gate and the source/drain. The individual parasitic capacitance components are extracted from TCAD simulation by varying the structural and material parameters of the device, which are then used for model validation. The fringing parasitic capacitance components are modeled using the elliptical integral method based on the distribution of the electric field lines. The proposed model accurately incorporates the substantial ( $\sim$ 30%) contribution of junction capacitance to the total parasitic capacitance. The model uses only one fitting parameter and is accurate across the device structural variations with only $\sim$ 1.2% error.

中文翻译：

---

纳米片 FET 中的寄生电容：不同组件的提取及其分析模型

这项工作提出了一种提取和分析模拟 Nanosheet FET 中寄生电容成分的方法。该模型全面考虑了栅极和源极/漏极之间的并联电容、边缘电容和结电容。通过改变器件的结构和材料参数，从 TCAD 仿真中提取各个寄生电容分量，然后将其用于模型验证。使用基于电场线分布的椭圆积分法对边缘寄生电容分量进行建模。所提出的模型准确地结合了实质性（ $\sim$ 30%）结电容对总寄生电容的贡献。该模型仅使用一个拟合参数，并且在整个设备结构变化中都是准确的，只需 $\sim$ 1.2% 误差。