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Systematic Study of the Incorporation of Quantum-Coupling 2-D Materials in the FET Gate/Channel Stack for Steep Subthreshold Slope
IEEE Transactions on Electron Devices ( IF 3.1 ) Pub Date : 2024-04-05 , DOI: 10.1109/ted.2024.3382221
Parameswari Raju 1 , Herwen Xu 2 , Hao Zhu 3 , Dimitris E. Ioannou 4 , Qiliang Li 1
Affiliation  

An alternative way to overcome the Boltzmann “tyranny” limit of the MOSFET subthreshold slope (SS) (60 mV/decade at room temperature) is to employ quantum coupling materials in the channel/gate-stack, in search of fast switching nanoscale devices. In this article, we explore the incorporation of a range of 2-D quantum materials in the FET gate/channel stack and find suitable combinations, which break the sub-60-mV/dec Boltzmann limit of minimum SS. We investigate the incorporation of layers of these materials in both the gate-stack and the channel, and their precise location and thickness, in order to find the parameter window of these quantum coupled devices for a steep SS. We also analyze the influence of channel strain and the doping of the “inserted” layer on the SS. We will present a brief overview based on our results of the different parameters that must be considered when designing the steep SS transistor, using the channel–gate-stack coupling concept.

中文翻译:

在 FET 栅极/通道堆栈中加入量子耦合二维材料以实现陡峭亚阈值斜率的系统研究

克服 MOSFET 亚阈值斜率 (SS)(室温下 60 mV/十年)的玻尔兹曼“暴政”限制的另一种方法是在通道/栅极堆叠中采用量子耦合材料,以寻找快速开关纳米级器件。在本文中,我们探索了一系列 2-D 量子材料在 FET 栅极/通道堆栈中的结合,并找到了合适的组合,这打破了最小 SS 的低于 60 mV/dec 玻尔兹曼极限。我们研究了这些材料层在栅极堆叠和沟道中的结合情况,以及它们的精确位置和厚度,以便找到这些量子耦合器件用于陡峭 SS 的参数窗口。我们还分析了沟道应变和“插入”层的掺杂对 SS 的影响。我们将根据使用通道-栅极-堆栈耦合概念设计陡峭 SS 晶体管时必须考虑的不同参数的结果进行简要概述。
更新日期:2024-04-05
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