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Passing Word Line-Induced Subthreshold Leakage Reduction Using a Partial Insulator in a Buried Channel Array Transistor
IEEE Transactions on Electron Devices ( IF 3.1 ) Pub Date : 2024-04-10 , DOI: 10.1109/ted.2024.3379963
Suyeon Kim 1 , Dong Young Kim 1 , Je Won Park 1 , Shinwook Kim 1 , Seungchan Lee 1 , Han Seung Jang 1 , Jinseok Park 1 , Sunyong Yoo 1 , Myoung Jin Lee 1
Affiliation  

As dynamic random access memory (DRAM) technologies continue to be downscaled, the partial isolation type buried channel array transistor (Pi-BCAT) structure has emerged as an innovative solution for the increasing challenges caused by leakage current adjacent to passing word lines (PWLs). This study reveals that the Pi-BCAT reduces leakage currents by 30% when compared to conventional BCAT structures. Our comprehensive simulations demonstrate that Pi-BCAT is resistant to temperature-induced leakage variations, confirming its significance in promoting consistent device performance and power management. The Pi-BCAT structure is predicted to be crucial in the advancement of DRAM reliability and efficiency, hence initiating further advancements in semiconductor technology.

中文翻译:

在埋入通道阵列晶体管中使用部分绝缘体来降低字线引起的亚阈值泄漏

随着动态随。这项研究表明,与传统的 BCAT 结构相比,Pi-BCAT 的漏电流降低了 30%。我们的全面仿真表明 Pi-BCAT 能够抵抗温度引起的泄漏变化,证实了其在促进一致的设备性能和电源管理方面的重要性。预计 Pi-BCAT 结构对于提高 DRAM 可靠性和效率至关重要,从而推动半导体技术的进一步进步。
更新日期:2024-04-10
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